mlsanityData to 14 Oct 2026

VFlow: Discovering Optimal Agentic Workflows for Verilog Generation

arXiv 2504.03723 ↗First posted 30 Mar 2025cs.AR cs.MAcited by 19

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

Hardware design automation faces challenges in generating high-quality Verilog code efficiently. This paper introduces VFlow, an automated framework that optimizes agentic workflows for Verilog code generation. Unlike traditional approaches relying on fixed prompts or manually designed flows, VFlow treats workflow discovery as a search over graph-structured LLM invocation sequences. It introduces a multi-population cooperative evolution (CEPE-MCTS) algorithm that balances multiple hardware objectives -- functional correctness, area, power, timing and token cost -- while sharing successful patterns and avoiding repeated failures. Integrated multi-level verification ensures syntactic correctness, functional behavior, and synthesizability. Experiments on VerilogEval and RTLLM2.0 show VFlow improves pass@1 by 20--30% over prompting baselines and closely matches designer-level area/power. Remarkably, VFlow enables small LLMs to outperform larger models with up to 10.9× ROI, offering a cost-effective solution for RTL design. This work paves the way for intelligent, automated hardware development, advancing LLM applications in EDA.

Key facts. Cited by 19 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 17 of its 28 references that are in the map. First posted on arXiv 30 Mar 2025.

Builds on

17 of 28 references.

Closest ancestors · 2

Same direction, newest first

  1. 2024AFlow: Automating Agentic Workflow Generation14 Oct
  2. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool15 Aug

Other references · 15

  1. 2020Language Models are Few-Shot Learnerscited by 32,419
  2. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
  3. 2022Self-Consistency Improves Chain of Thought Reasoning in Language Modelscited by 5,708
  4. 2023Self-Refine: Iterative Refinement with Self-Feedbackcited by 3,442
  5. 2023DSPy: Compiling Declarative Language Model Calls into Self-Improving Pipelinescited by 832
  6. 2024Automated Design of Agentic Systemscited by 407
  7. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  8. 2023Unleashing the Emergent Cognitive Synergy in Large Language Models: A Task-Solving Agent through Multi-Persona Self-Collaborationcited by 251
  9. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  10. 2025Multi-agent Architecture Search via Agentic Supernetcited by 179
  11. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  12. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
3 more
  1. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  2. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 25
  3. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 23

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 7; 2026: 12.

19 papers.

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  1. 2025Advances and Challenges in Foundation Agents: From Brain-Inspired Intelligence to Evolutionary, Collaborative, and Safe Systemscited by 126
  2. 2026From Static Templates to Dynamic Runtime Graphs: A Survey of Workflow Optimization for LLM Agentscited by 24
  3. 2025Graph-Augmented Large Language Model Agents: Current Progress and Future Prospectscited by 14
  4. 2025Scheduling Your LLM Reinforcement Learning with Reasoning Treescited by 12
  5. 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimizationcited by 11
  6. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  7. 2025Self-Attention to Operator Learning-based 3D-IC Thermal Simulationcited by 7
  8. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  9. 2025Compound AI Systems Optimization: A Survey of Methods, Challenges, and Future Directionscited by 4
  10. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
  11. 2026Graph Engineering in the Era of LLM Agents: From Individual Intelligence to System Intelligencecited by 3
  12. 2026Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curationcited by 2
7 more
  1. 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocolscited by 1
  2. 2026Learning Neural Operators from Partial Observations via Latent Autoregressive Modelingcited by 1
  3. 2026HGATSolver: A Heterogeneous Graph Attention Solver for Fluid-Structure Interactioncited by 0
  4. 2026ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestrationcited by 0
  5. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
  6. 2026PCBnet: A Dataset and Automatic Construction of SPICE Netlists from Schematic Imagescited by 0
  7. 2026MoFlow: Multi-Objective Agentic Workflow Generationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  2. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
  3. 2026Exploring the Agentic Frontier of Verilog Code Generation
  4. 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
  5. 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
  6. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
  7. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
  8. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs