mlsanityData to 14 Oct 2026

VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

arXiv 2505.20302 ↗First posted 16 May 2025cs.PL cs.AI cs.LOcited by 15

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Abstract (arXiv)

This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at hrefhttps://github.com/wilyub/VeriThoughtsthis URL.

Key facts. Cited by 15 papers in the map (data through 14 Oct 2026). Builds on 18 of its 27 references that are in the map. First posted on arXiv 16 May 2025.

Builds on

18 of 27 references.

References · 18

  1. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  2. 2023Code Llama: Open Foundation Models for Codecited by 2,139
  3. 2024LlamaFactory: Unified Efficient Fine-Tuning of 100+ Language Modelscited by 1,464
  4. 2020CodeBERT: A Pre-Trained Model for Programming and Natural Languagescited by 1,310
  5. 2021CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generationcited by 906
  6. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 885
  7. 2022InCoder: A Generative Model for Code Infilling and Synthesiscited by 498
  8. 2023Large Language Models for Software Engineering: A Systematic Literature Reviewcited by 399
  9. 2023The Impact of AI on Developer Productivity: Evidence from GitHub Copilotcited by 274
  10. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  11. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  12. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
6 more
  1. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  2. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  3. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  4. 2023Chain-of-Thought in Neural Code Generation: From and For Lightweight Language Modelscited by 27
  5. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  6. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 5; 2026: 10.

15 papers.

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  1. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  2. 2025TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generationcited by 4
  3. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
  4. 2026InCoder-32B-Thinking: Industrial Code World Model for Thinkingcited by 4
  5. 2025Automated Multi-Agent Workflows for RTL Designcited by 3
  6. 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocolscited by 1
  7. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  8. 2026VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generationcited by 1
  9. 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
  10. 2026Exploring the Agentic Frontier of Verilog Code Generationcited by 1
  11. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  12. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
3 more
  1. 2026Benchmarking LLMs for Verilog Design Flowscited by 0
  2. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
  3. 2026CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learningcited by 0