mlsanityData to 7 Oct 2026

Agentic Hardware Design as Repository-Level Code Evolution

arXiv 2606.28279 ↗First posted 26 Jun 2026cs.AR cs.AIcited by 6

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

We present HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution. A Markdown harness is compiled into a project pack containing domain knowledge, an executable evaluator, an acceptance predicate, and a git/runtime policy; a hands-free agent loop then evolves an isolated git worktree, using repository operations for state management, tracing, and replay. This extends prior works of repository-scale self-evolution from EDA software systems, to hardware-design artifacts themselves. We evaluate our approach on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories, achieving 100% benchmark completion across all suites with a fully hands-free agentic loop. However, we do not claim that agentic AI for hardware design is solved: these benchmarks are controlled proxies for a much broader engineering problem in chip design. Section~refsec:discuss examines the limitations of the current study and highlights open research challenges.

Key facts. Cited by 6 papers in the map (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 21 of its 24 references that are in the map. First posted on arXiv 26 Jun 2026.

Builds on

21 of 24 references.

Closest ancestors · 5

Same direction, newest first

  1. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs10 Feb
  2. 2025Autonomous Code Evolution Meets NP-Completeness9 Sep
  3. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification17 Jun
  4. 2025AlphaEvolve: A coding agent for scientific and algorithmic discovery16 Jun
  5. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool15 Aug

Other references · 16

  1. 2023SWE-bench: Can Language Models Resolve Real-World GitHub Issues?cited by 3,193
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  3. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  4. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  5. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  6. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  7. 2024SWE-Bench+: Enhanced Coding Benchmark for LLMscited by 95
  8. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  9. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  10. 2025Are "Solved Issues" in SWE-bench Really Solved Correctly? An Empirical Studycited by 47
  11. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  12. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 30
4 more
  1. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  2. 2025Git Context Controller: Manage the Context of LLM-based Agents like Gitcited by 13
  3. 2025EvoGit: Decentralized Code Evolution via Git-Based Multi-Agent Collaborationcited by 9
  4. 2026Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABCcited by 6

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 6.

6 papers.

  1. 2026CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agentscited by 0
  2. 2026ETAS: An Effect-Typed Language for Agent Systemscited by 0
  3. 2026ChipMEM: Verification-Grounded Memory for EDA Agentscited by 0
  4. 2026Automatic Harness Evolution for Hardware Design Verification: Can LLMs Consolidate Gains Across Discovered Harnesses?cited by 0
  5. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0
  6. 2026LEGO-Anything: Coding Agents for 3D Scene Reconstructioncited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
  2. 2026Agentic Architect: An Agentic AI Framework for Architecture Design Exploration and Optimization
  3. 2026From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis
  4. 2026Benchmarking AI Agents for Hardware Design Automation via MCP Tool Calling
  5. 2026Coco: An Agentic Copilot for the Hardware--Software Co-Design Lifecycle
  6. 2026RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation
  7. 2025ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
  8. 2026Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification