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RuC: HDL-Agnostic Rule Completion Benchmark Generation

arXiv 2604.27780 ↗First posted 30 Apr 2026cs.AR cs.AIcited by 0

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Abstract (arXiv)

Large Language Models (LLMs) have rapidly improved in performance across code-related tasks, making their integration into Register Transfer Level (RTL) development increasingly attractive. Mimicking the behavior of inline code assistants, many benchmarks evaluate LLMs' capabilities in code completion, either assessing the generation of entire hardware modules or the completion of a single line within a module. However both of these approaches lack the ability to control the granularity of the code-completion sample size and the syntactic range of completions. To overcome these limitations, we present a framework for language-agnostic rule completion (RuC), a grammar-driven, rule-selectable benchmark generator that automatically produces RTL code-completion tasks from a set of input hardware description sources. RuC uses the target Hardware Description Language (HDL) grammar to mask syntactically defined code regions and prompts a model to regenerate them using the surrounding unmasked code as context, enabling a controlled and scalable evaluation of the domain-specific model's code-understanding capabilities, ranging from assignments to the reconstruction of entire logic blocks. We use RuC to generate two SystemVerilog rule-completion benchmarks from the Tiny Tapeout shuttle TT07 and the CVE2 RISC-V core to demonstrate RuC's applicability to a broad range of designs, and conduct a comparative study of the code completion capabilities of modern open-source LLMs across diverse settings. Results indicate that completion performance strongly depends on the model type, the grammatical structure of the masked region, and the prompting strategy. Specifically, the highest scores are obtained with Fill-in-the-Middle (FIM) prompting. These findings highlight the value of grammar-driven, arbitrarily granular benchmarks for meaningful evaluation of LLM capabilities in RTL development workflows.

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References · 13

  1. 2024A Survey on Large Language Models for Code Generationcited by 646
  2. 2022InCoder: A Generative Model for Code Infilling and Synthesiscited by 492
  3. 2022Efficient Training of Language Models to Fill in the Middlecited by 248
  4. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  5. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  6. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  7. 2023CodeScore: Evaluating Code Generation by Learning Code Executioncited by 66
  8. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 41
  9. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  10. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 25
  11. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
  12. 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generationcited by 3
1 more
  1. 2025Extending Fill-In-the-Middle with Instructions for Steerable Code Completioncited by 2

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