mlsanityData to 14 Oct 2026

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation

arXiv 2504.15659 ↗First posted 22 Apr 2025cs.AR cs.AI cs.CLcited by 13

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Abstract (arXiv)

Recent advances in Large Language Models (LLMs) have sparked growing interest in applying them to Electronic Design Automation (EDA) tasks, particularly Register Transfer Level (RTL) code generation. While several RTL datasets have been introduced, most focus on syntactic validity rather than functional validation with tests, leading to training examples that compile but may not implement the intended behavior. We present VERICODER, a model for RTL code generation fine-tuned on a dataset validated for functional correctness. This fine-tuning dataset is constructed using a novel methodology that combines unit test generation with feedback-directed refinement. Given a natural language specification and an initial RTL design, we prompt a teacher model (GPT-4o-mini) to generate unit tests and iteratively revise the RTL design based on its simulation results using the generated tests. If necessary, the teacher model also updates the tests to ensure they comply with the natural language specification. As a result of this process, every example in our dataset is functionally validated, consisting of a natural language description, an RTL implementation, and passing tests. Fine-tuned on this dataset of 125,777 examples, VERICODER achieves state-of-the-art metrics in functional correctness on VerilogEval and RTLLM, with relative gains of up to 71.7% and 27.4%, respectively. An ablation study further shows that models trained on our functionally validated dataset outperform those trained on functionally non-validated datasets, underscoring the importance of high-quality datasets in RTL code generation. Our code, data, and models are publicly available at https://github.com/Anjiang-Wei/VeriCoder

Key facts. Cited by 13 papers in the map (data through 14 Oct 2026). Builds on 35 of its 46 references that are in the map. First posted on arXiv 22 Apr 2025.

Builds on

35 of 46 references.

References · 35

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,380
  2. 2023SWE-bench: Can Language Models Resolve Real-World GitHub Issues?cited by 3,373
  3. 2023StarCoder: may the source be with you!cited by 799
  4. 2024StarCoder 2 and The Stack v2: The Next Generationcited by 502
  5. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  6. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  7. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  8. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  9. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  10. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  11. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  12. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
23 more
  1. 2024Enhancing Code LLMs with Reinforcement Learning in Code Generation: A Surveycited by 83
  2. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  3. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  4. 2023nl2spec: Interactively Translating Unstructured Natural Language to Temporal Logics with Large Language Modelscited by 60
  5. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  6. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  7. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  8. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  9. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  10. 2024CoRNStack: High-Quality Contrastive Data for Better Code Retrieval and Rerankingcited by 37
  11. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  12. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  13. 2024AlphaVerus: Bootstrapping Formally Verified Code Generation through Self-Improving Translation and Treefinementcited by 35
  14. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  15. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  16. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  17. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  18. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  19. 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
  20. 2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10
  21. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentationcited by 7
  22. 2024Are LLMs Any Good for High-Level Synthesis?cited by 6
  23. 2024From English to ASIC: Hardware Implementation with Large Language Modelcited by 3

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 8; 2026: 5.

13 papers.

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  1. 2025Astra: A Multi-Agent System for GPU Kernel Performance Optimizationcited by 51
  2. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  3. 2025SuperCoder: Assembly Program Superoptimization with Large Language Modelscited by 6
  4. 2026Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generationcited by 3
  5. 2026SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generationcited by 2
  6. 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosiscited by 1
  7. 2025The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generationcited by 1
  8. 2025Breaking Memorization Barriers in LLM Code Fine-Tuning via Information Bottleneck for Improved Generalizationcited by 1
  9. 2025Learning to Debug: LLM-Organized Knowledge Trees for Solving RTL Assertion Failurescited by 1
  10. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflowcited by 1
  11. 2025Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automationcited by 0
  12. 2026EstRTL: Functional Estimation Guided RTL Code Generationcited by 0
1 more
  1. 2026CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generationcited by 0