mlsanityData to 14 Oct 2026

VerilogReader: LLM-Aided Hardware Test Generation

arXiv 2406.04373 ↗First posted 3 Jun 2024cs.SE cs.AIcited by 17

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Abstract (arXiv)

Test generation has been a critical and labor-intensive process in hardware design verification. Recently, the emergence of Large Language Model (LLM) with their advanced understanding and inference capabilities, has introduced a novel approach. In this work, we investigate the integration of LLM into the Coverage Directed Test Generation (CDG) process, where the LLM functions as a Verilog Reader. It accurately grasps the code logic, thereby generating stimuli that can reach unexplored code branches. We compare our framework with random testing, using our self-designed Verilog benchmark suite. Experiments demonstrate that our framework outperforms random testing on designs within the LLM's comprehension scope. Our work also proposes prompt engineering optimizations to augment LLM's understanding scope and accuracy.

Key facts. Cited by 17 papers in the map (data through 14 Oct 2026). Builds on 6 of its 20 references that are in the map. First posted on arXiv 3 Jun 2024.

Builds on

6 of 20 references.

References · 6

  1. 2023GPT-4 Technical Reportcited by 18,396
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  3. 2023Large Language Models on Graphs: A Comprehensive Surveycited by 192
  4. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  5. 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
  6. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 23

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 1; 2025: 10; 2026: 6.

17 papers.

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  1. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  2. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  3. 2025HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionscited by 5
  4. 2025Using GUI Agent for Electronic Design Automationcited by 5
  5. 2025TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generationcited by 4
  6. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  7. 2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2
  8. 2026RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revisioncited by 2
  9. 2025Proof2Silicon: Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learningcited by 1
  10. 2025Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middlewarecited by 1
  11. 2026VeriPilot: An LLM-Powered Verilog Debugging Frameworkcited by 1
  12. 2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Languagecited by 0
5 more
  1. 2025Graph Neural Networks Based Analog Circuit Link Predictioncited by 0
  2. 2025DUET: Agentic Design Understanding via Experimentation and Testingcited by 0
  3. 2026BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Modelscited by 0
  4. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
  5. 2026A Survey on LLM-Integrated Hardware Design Verificationcited by 0