mlsanityData to 7 Oct 2026

ChipGPT: How far are we from natural language hardware design

arXiv 2305.14019 ↗First posted 23 May 2023cs.AI cs.AR cs.PLcited by 101

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Abstract (arXiv)

As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automated design environment that explores LLMs to generate hardware logic designs from natural language specifications. To realize a more accessible and efficient chip development flow, we present a scalable four-stage zero-code logic design framework based on LLMs without retraining or finetuning. At first, the demo, ChipGPT, begins by generating prompts for the LLM, which then produces initial Verilog programs. Second, an output manager corrects and optimizes these programs before collecting them into the final design space. Eventually, ChipGPT will search through this space to select the optimal design under the target metrics. The evaluation sheds some light on whether LLMs can generate correct and complete hardware logic designs described by natural language for some specifications. It is shown that ChipGPT improves programmability, and controllability, and shows broader design optimization space compared to prior work and native LLMs alone.

Key facts. Cited by 101 papers in the map (data through 7 Oct 2026). Builds on 13 of its 27 references that are in the map. First posted on arXiv 23 May 2023.

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13 of 27 references.

References · 13

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,084
  2. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,302
  3. 2019Parameter-Efficient Transfer Learning for NLPcited by 4,195
  4. 2022Least-to-Most Prompting Enables Complex Reasoning in Large Language Modelscited by 1,397
  5. 2020CodeBERT: A Pre-Trained Model for Programming and Natural Languagescited by 1,286
  6. 2014How transferable are features in deep neural networks?cited by 1,216
  7. 2022Large Language Models Are Human-Level Prompt Engineerscited by 1,020
  8. 2021CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generationcited by 890
  9. 2023Visual ChatGPT: Talking, Drawing and Editing with Visual Foundation Modelscited by 659
  10. 2020GraphCodeBERT: Pre-training Code Representations with Data Flowcited by 600
  11. 2022UniXcoder: Unified Cross-Modal Pre-training for Code Representationcited by 355
  12. 2021ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representationcited by 21
1 more
  1. 2018BoSy: An Experimentation Framework for Bounded Synthesiscited by 8

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 6; 2024: 27; 2025: 48; 2026: 20.

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  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  3. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  4. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  5. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  6. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  7. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  8. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  9. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  10. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  11. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  12. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
38 more
  1. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  2. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  3. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  4. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  5. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  6. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  7. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
  8. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  9. 2024ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generationcited by 15
  10. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  11. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  12. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 14
  13. 2024EEE-Bench: A Comprehensive Multimodal Electrical And Electronics Engineering Benchmarkcited by 14
  14. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  15. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  16. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  17. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 12
  18. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  19. 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
  20. 2024All Artificial, Less Intelligence: GenAI through the Lens of Formal Verificationcited by 11
  21. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  22. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  23. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  24. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  25. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  26. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  27. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  28. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
  29. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 8
  30. 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
  31. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentationcited by 7
  32. 2025AI Agents for Photonic Integrated Circuit Design Automationcited by 7
  33. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  34. 2024Are LLMs Any Good for High-Level Synthesis?cited by 6
  35. 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
  36. 2024SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generationcited by 5
  37. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
  38. 2025BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detectioncited by 5

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