mlsanityData to 14 Oct 2026

VeriPilot: An LLM-Powered Verilog Debugging Framework

arXiv 2606.23759 ↗First posted 22 Jun 2026cs.AR cs.AI cs.SEcited by 1

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Abstract (arXiv)

Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent advances in Large Language Models (LLMs) have enabled automated debugging; however, most existing approaches rely solely on test outputs and compiler feedback in an end-to-end manner, limiting their effectiveness on complex bugs. A key challenge is that the root cause of an error may be far removed from its observable outputs, making it difficult for LLMs to trace long dependency chains in code. This challenge is further exacerbated in large codebases, where long context lengths hinder efficient reasoning. To address these limitations, we propose VeriPilot, an LLM-powered debugging framework that leverages golden reference models to enable fine-grained bug localization and repair. VeriPilot goes beyond output-level comparison by aligning internal variable semantics between the Verilog design and its corresponding golden model through LLM-based analysis. It then performs step-by-step signal tracing using Control-Data-Flow Graphs (CDFGs) derived from static analysis, identifying a minimal set of suspicious code regions along with their correct counterparts from the golden model. These structured insights are subsequently provided to the LLM to guide reasoning and automated code repair. Experimental results on the Comprehensive Verilog Design Problems (CVDP) benchmark from NVIDIA demonstrate that VeriPilot improves the repair success rate of GPT-4o from 54.3% to 85.71%, significantly enhancing both bug localization accuracy and repair effectiveness for complex Verilog designs. The source code and benchmark are publicly available at Github https://github.com/YihanWn/VeriPilot.git.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 27 of its 46 references that are in the map. First posted on arXiv 22 Jun 2026.

Builds on

27 of 46 references.

References · 27

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  3. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  4. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  5. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  6. 2023A Survey of Learning-based Automated Program Repaircited by 55
  7. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  8. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  9. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  10. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
  11. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  12. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
15 more
  1. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 17
  2. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  3. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  4. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
  5. 2025VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correctioncited by 12
  6. 2024LLM-Aided Efficient Hardware Design Automationcited by 11
  7. 2025From Large to Small: Transferring CUDA Optimization Expertise via Reasoning Graphcited by 10
  8. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  9. 2021Verifix: Verified Repair of Programming Assignmentscited by 7
  10. 2025LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Modelscited by 7
  11. 2025BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesiscited by 6
  12. 2024Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Promptingcited by 4
  13. 2025SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Designcited by 4
  14. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoningcited by 4
  15. 2025hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generationcited by 2

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 1.

1 paper.

  1. 2026A Survey on LLM-Integrated Hardware Design Verificationcited by 0

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  1. 2025HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
  2. 2024Debug like a Human: A Large Language Model Debugger via Verifying Runtime Execution Step-by-step
  3. 2026LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns
  4. 2025Exploring the Potential and Limitations of Large Language Models for Novice Program Fault Localization ↗
  5. 2026Debug Like a Human: Scaling LLM-based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing
  6. 2025FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
  7. 2024Demystifying Faulty Code with LLM: Step-by-Step Reasoning for Explainable Fault Localization
  8. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs