mlsanityData to 7 Oct 2026

BetterV: Controlled Verilog Generation with Discriminative Guidance

arXiv 2402.03375 ↗First posted 3 Feb 2024cs.AI cs.PLcited by 99

Not on the map. Why?

Abstract (arXiv)

Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tune the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.

Key facts. Cited by 99 papers in the map (data through 7 Oct 2026). Builds on 24 of its 30 references that are in the map. First posted on arXiv 3 Feb 2024.

Builds on

24 of 30 references.

References · 24

  1. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  2. 2016SGDR: Stochastic Gradient Descent with Warm Restartscited by 4,993
  3. 2023Qwen Technical Reportcited by 3,273
  4. 2023Code Llama: Open Foundation Models for Codecited by 2,105
  5. 2019ZeRO: Memory Optimizations Toward Training Trillion Parameter Modelscited by 1,278
  6. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
  7. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 876
  8. 2019Plug and Play Language Models: A Simple Approach to Controlled Text Generationcited by 793
  9. 2019CTRL: A Conditional Transformer Language Model for Controllable Generationcited by 754
  10. 2021DExperts: Decoding-Time Controlled Text Generation with Experts and Anti-Expertscited by 434
  11. 2020GeDi: Generative Discriminator Guided Sequence Generationcited by 377
  12. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
12 more
  1. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  2. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  3. 2022A Survey of Controllable Text Generation using Transformer-based Pre-trained Language Modelscited by 128
  4. 2023CodeGen2: Lessons for Training LLMs on Programming and Natural Languagescited by 124
  5. 2018Learning to Write with Cooperative Discriminatorscited by 119
  6. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  7. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  8. 2023DeepSpeed-Chat: Easy, Fast and Affordable RLHF Training of ChatGPT-like Models at All Scalescited by 107
  9. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  10. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  11. 2020Discriminative Adversarial Search for Abstractive Summarizationcited by 14
  12. 2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 21; 2025: 55; 2026: 23.

99 papers.

Sort:

By area:

  1. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  2. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  3. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  4. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  5. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  6. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  7. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  8. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  9. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  10. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  11. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  12. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
38 more
  1. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  2. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  3. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  4. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  5. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  6. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  7. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  8. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  9. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  10. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  11. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  12. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  13. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
  14. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  15. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  16. 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10
  17. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  18. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  19. 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
  20. 2025QAgent: An LLM-based Multi-Agent System for Autonomous OpenQASM programmingcited by 9
  21. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  22. 2024Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilogcited by 8
  23. 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
  24. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
  25. 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
  26. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  27. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentationcited by 7
  28. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  29. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 6
  30. 2024Circuit Transformer: A Transformer That Preserves Logical Equivalencecited by 5
  31. 2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
  32. 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Modelscited by 5
  33. 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 5
  34. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMscited by 4
  35. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
  36. 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
  37. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  38. 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generationcited by 4

50 most cited of 99 All 99 (JSON)