mlsanityData to 7 Oct 2026

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

arXiv 2311.16543 ↗First posted 28 Nov 2023cs.ARcited by 98

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Cited by 22 in LLM agents and tool use, but placed by its own abstract, which didn’t fit.

Abstract (arXiv)

This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities, our analysis indicates that approximately 55% of errors in LLM-generated Verilog are syntax-related, leading to compilation failures. To tackle this issue, we introduce a novel debugging framework that employs Retrieval-Augmented Generation (RAG) and ReAct prompting, enabling LLMs to act as autonomous agents in interactively debugging the code with feedback. This framework demonstrates exceptional proficiency in resolving syntax errors, successfully correcting about 98.5% of compilation errors in our debugging dataset, comprising 212 erroneous implementations derived from the VerilogEval benchmark. Our method leads to 32.3% and 10.1% increase in pass@1 success rates in the VerilogEval-Machine and VerilogEval-Human benchmarks, respectively.

Key facts. Cited by 98 papers in the map (data through 7 Oct 2026). First posted on arXiv 28 Nov 2023.

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 1; 2024: 29; 2025: 46; 2026: 22.

98 papers.

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  1. 2024A Survey on the Memory Mechanism of Large Language Model based Agentscited by 622
  2. 2024Retrieval-Augmented Generation for AI-Generated Content: A Surveycited by 352
  3. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  4. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  5. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  6. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  7. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  8. 2024KARMA: Augmenting Embodied AI Agents with Long-and-short Term Memory Systemscited by 38
  9. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  10. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  11. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  12. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
38 more
  1. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  2. 2025Retrieval-Augmented Code Generation: A Survey with Focus on Repository-Level Approachescited by 20
  3. 2024Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruningcited by 19
  4. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  5. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  6. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
  7. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  8. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  9. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  10. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  11. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 12
  12. 2025VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correctioncited by 12
  13. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  14. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  15. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 9
  16. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  17. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  18. 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
  19. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
  20. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 8
  21. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  22. 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
  23. 2024SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detectioncited by 7
  24. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
  25. 2025Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlistscited by 7
  26. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  27. 2025cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolutioncited by 7
  28. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 6
  29. 2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6
  30. 2024Using a Feedback Loop for LLM-based Infrastructure as Code Generationcited by 5
  31. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
  32. 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Modelscited by 5
  33. 2025Using GUI Agent for Electronic Design Automationcited by 5
  34. 2024Enhance the Robustness of Text-Centric Multimodal Alignmentscited by 4
  35. 2024SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Modelcited by 4
  36. 2025Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automationcited by 4
  37. 2025Uncertainty Profiles for LLMs: Uncertainty Source Decomposition and Adaptive Model-Metric Selectioncited by 4
  38. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4

50 most cited of 98 All 98 (JSON)

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  1. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  2. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation
  3. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  4. 2025Fully Autonomous Programming using Iterative Multi-Agent Debugging with Large Language Models
  5. 2025BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis
  6. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
  7. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
  8. 2024RGD: Multi-LLM Based Agent Debugger via Refinement and Generation Guidance