mlsanityData to 7 Oct 2026

MAGE: A Multi-Agent Engine for Automated RTL Code Generation

arXiv 2412.07822 ↗First posted 10 Dec 2024cs.AR cs.LGcited by 31

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

The automatic generation of RTL code (e.g., Verilog) through natural language instructions has emerged as a promising direction with the advancement of large language models (LLMs). However, producing RTL code that is both syntactically and functionally correct remains a significant challenge. Existing single-LLM-agent approaches face substantial limitations because they must navigate between various programming languages and handle intricate generation, verification, and modification tasks. To address these challenges, this paper introduces MAGE, the first open-source multi-agent AI system designed for robust and accurate Verilog RTL code generation. We propose a novel high-temperature RTL candidate sampling and debugging system that effectively explores the space of code candidates and significantly improves the quality of the candidates. Furthermore, we design a novel Verilog-state checkpoint checking mechanism that enables early detection of functional errors and delivers precise feedback for targeted fixes, significantly enhancing the functional correctness of the generated RTL code. MAGE achieves a 95.7% rate of syntactic and functional correctness code generation on VerilogEval-Human 2 benchmark, surpassing the state-of-the-art Claude-3.5-sonnet by 23.3 %, demonstrating a robust and reliable approach for AI-driven RTL design workflows.

Key facts. Cited by 31 papers in the map (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 14 of its 34 references that are in the map. First posted on arXiv 10 Dec 2024.

Builds on

14 of 34 references.

Closest ancestors · 2

Same direction, newest first

  1. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool15 Aug
  2. 2023AgentCoder: Multi-Agent-based Code Generation with Iterative Testing and Optimisation20 Dec

Other references · 12

  1. 2023GPT-4 Technical Reportcited by 18,132
  2. 2023CodeGeeX: A Pre-Trained Model for Code Generation with Multilingual Benchmarking on HumanEval-Xcited by 294
  3. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  4. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  5. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  6. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  7. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  8. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  9. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  10. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  11. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  12. 2024Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesiscited by 5

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 9; 2026: 22.

31 papers.

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  1. 2026Code as Agent Harnesscited by 40
  2. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  3. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMscited by 12
  4. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  5. 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Designcited by 7
  6. 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
  7. 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 5
  8. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoningcited by 4
  9. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  10. 2026LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generationcited by 4
  11. 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generationcited by 4
  12. 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
19 more
  1. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
  2. 2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Promptscited by 2
  3. 2025Tool-RoCo: An Agent-as-Tool Self-organization Large Language Model Benchmark in Multi-robot Cooperationcited by 2
  4. 2025Assessing Large Language Models in Generating RTL Design Specificationscited by 2
  5. 2026Rollout-Training Co-Design for Efficient LLM-Based Multi-Agent Reinforcement Learningcited by 2
  6. 2026RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revisioncited by 2
  7. 2025Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middlewarecited by 1
  8. 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
  9. 2026QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generationcited by 1
  10. 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
  11. 2026AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuitscited by 1
  12. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflowcited by 1
  13. 2026ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimizationcited by 0
  14. 2026IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolutioncited by 0
  15. 2026LLM4RTL: Tool-Assisted LLM for RTL Generationcited by 0
  16. 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinementcited by 0
  17. 2026CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generationcited by 0
  18. 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedbackcited by 0
  19. 2026Can Agents Design Better Chips with a Higher Level Abstraction?cited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2024EDA-Aware RTL Generation with Large Language Models
  2. 2026ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
  3. 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI
  4. 2025Automated Multi-Agent Workflows for RTL Design
  5. 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
  6. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
  7. 2025PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
  8. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification