mlsanityData to 14 Oct 2026

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA

arXiv 2308.10204 ↗First posted 20 Aug 2023cs.AR cs.AIcited by 122

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

The integration of a complex set of Electronic Design Automation (EDA) tools to enhance interoperability is a critical concern for circuit designers. Recent advancements in large language models (LLMs) have showcased their exceptional capabilities in natural language processing and comprehension, offering a novel approach to interfacing with EDA tools. This research paper introduces ChatEDA, an autonomous agent for EDA empowered by an LLM, AutoMage, complemented by EDA tools serving as executors. ChatEDA streamlines the design flow from the Register-Transfer Level (RTL) to the Graphic Data System Version II (GDSII) by effectively managing task decomposition, script generation, and task execution. Through comprehensive experimental evaluations, ChatEDA has demonstrated its proficiency in handling diverse requirements, and our fine-tuned AutoMage model has exhibited superior performance compared to GPT-4 and other similar LLMs.

Key facts. Cited by 122 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 32 of its 50 references that are in the map. First posted on arXiv 20 Aug 2023.

Builds on

32 of 50 references.

References · 32

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  2. 2020Language Models are Few-Shot Learnerscited by 32,419
  3. 2023GPT-4 Technical Reportcited by 18,396
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20 more
  1. 2021Finetuned Language Models Are Zero-Shot Learnerscited by 3,780
  2. 2023QLoRA: Efficient Finetuning of Quantized LLMscited by 3,418
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Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2023: 7; 2024: 33; 2025: 47; 2026: 35.

122 papers.

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  1. 2023A Survey on Large Language Model based Autonomous Agentscited by 2,242
  2. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  3. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  4. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 84
  5. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  6. 2023Algorithm Evolution Using Large Language Modelcited by 53
  7. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  8. 2025SciToolAgent: A Knowledge Graph-Driven Scientific Agent for Multi-Tool Integrationcited by 43
  9. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  10. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  11. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 37
  12. 2025From Language to Action: A Review of Large Language Models as Autonomous Agents and Tool Userscited by 32
38 more
  1. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  2. 2023Large Language Model for Multi-objective Evolutionary Optimizationcited by 29
  3. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  4. 2024Securing Large Language Models: Addressing Bias, Misinformation, and Prompt Attackscited by 26
  5. 2024AMSNet: Netlist Dataset for AMS Circuitscited by 25
  6. 2024Large Language Models for Manufacturingcited by 24
  7. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  8. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
  9. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  10. 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Modelscited by 18
  11. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  12. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 15
  13. 2024EEE-Bench: A Comprehensive Multimodal Electrical And Electronics Engineering Benchmarkcited by 15
  14. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  15. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 15
  16. 2023Towards Responsible Generative AI: A Reference Architecture for Designing Foundation Model based Agentscited by 14
  17. 2025ORFS-agent: Tool-Using Agents for Chip Design Optimizationcited by 14
  18. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  19. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 13
  20. 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 13
  21. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  22. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  23. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  24. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  25. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  26. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
  27. 2024Causal Agent based on Large Language Modelcited by 10
  28. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  29. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 10
  30. 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
  31. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  32. 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
  33. 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
  34. 2024SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detectioncited by 7
  35. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
  36. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 7
  37. 2025AI Agents for Photonic Integrated Circuit Design Automationcited by 7
  38. 2024ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolationcited by 6

50 most cited of 122 All 122 (JSON)

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  1. 2025Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation
  2. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)
  3. 2025JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation
  4. 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts
  5. 2024Ask-EDA: A Design Assistant Empowered by LLM, Hybrid RAG and Abbreviation De-hallucination
  6. 2026Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification
  7. 2026LEGO: An LLM Skill-Based Front-End Design Generation Platform
  8. 2026AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents