mlsanityData to 14 Oct 2026

REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models

arXiv 2510.21407 ↗First posted 24 Oct 2025cs.NE cs.AI cs.SEcited by 4

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Abstract (arXiv)

Large Language Models (LLMs) are used for Register-Transfer Level (RTL) code generation, but they face two main challenges: functional correctness and Power, Performance, and Area (PPA) optimization. Iterative, feedback-based methods partially address these, but they are limited to local search, hindering the discovery of a global optimum. This paper introduces REvolution, a framework that combines Evolutionary Computation (EC) with LLMs for automatic RTL generation and optimization. REvolution evolves a population of candidates in parallel, each defined by a design strategy, RTL implementation, and evaluation feedback. The framework includes a dual-population algorithm that divides candidates into Fail and Success groups for bug fixing and PPA optimization, respectively. An adaptive mechanism further improves search efficiency by dynamically adjusting the selection probability of each prompt strategy according to its success rate. Experiments on the VerilogEval and RTLLM benchmarks show that REvolution increased the initial pass rate of various LLMs by up to 24.0 percentage points. The DeepSeek-V3 model achieved a final pass rate of 95.5%, comparable to state-of-the-art results, without the need for separate training or domain-specific tools. Additionally, the generated RTL designs showed significant PPA improvements over reference designs. This work introduces a new RTL design approach by combining LLMs' generative capabilities with EC's broad search power, overcoming the local-search limitations of previous methods.

Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Builds on 20 of its 31 references that are in the map. First posted on arXiv 24 Oct 2025.

Builds on

20 of 31 references.

References · 20

  1. 2024The Llama 3 Herd of Modelscited by 14,715
  2. 2025AlphaEvolve: A coding agent for scientific and algorithmic discoverycited by 867
  3. 2024Evolution of Heuristics: Towards Efficient Automatic Algorithm Design Using Large Language Modelcited by 268
  4. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  5. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  6. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  7. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  8. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  9. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  10. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  11. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  12. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
8 more
  1. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  2. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  3. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  4. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  5. 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
  6. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  7. 2025Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Designcited by 6
  8. 2025SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Designcited by 4

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 4.

4 papers.

  1. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  2. 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
  3. 2026Alpha-RTL: Test-Time Training for RTL Hardware Optimizationcited by 2
  4. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0