mlsanityData to 13 Oct 2026

Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware

arXiv 2510.08664 ↗First posted 9 Oct 2025cs.SE cs.AIcited by 1

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Abstract (arXiv)

LLM-based RTL generation is an interesting research direction, as it holds the potential to liberate the least automated stage in the current chip design. However, due to the substantial semantic gap between high-level specifications and RTL, coupled with limited training data, existing models struggle with generation accuracy. Drawing on human experience, design with verification helps improving accuracy. However, as the RTL testbench data are even more scarce, it is not friendly for LLMs. Although LLMs excel at higher-level languages like Python/C, they have a huge semantic gap from RTL. When implementing the same functionality, Python/C code and hardware code differ significantly in the spatiotemporal granularity, requiring the LLM not only to consider high-level functional semantics but also to ensure the low-level details align with the circuit code. It is not an easy task. In this paper, we propose a function abstracted verifiable middleware (Faver) that streamlines RTL verification in LLM-based workflows. By mixing LLM-friendly code structures with a rule-based template, Faver decouples the details of circuit verification, allowing the LLM to focus on the functionality itself. In our experiments on the SFT model and open-source models, Faver improved the model's generation accuracy by up to 14%.

Key facts. Cited by 1 paper in the map (data through 13 Oct 2026). Builds on 14 of its 25 references that are in the map. First posted on arXiv 9 Oct 2025.

Builds on

14 of 25 references.

References · 14

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,231
  2. 2023CRITIC: Large Language Models Can Self-Correct with Tool-Interactive Critiquingcited by 764
  3. 2022CodeT: Code Generation with Generated Testscited by 377
  4. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  5. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  6. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  7. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  8. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  9. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  10. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  11. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  12. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
2 more
  1. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 17
  2. 2025PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verificationcited by 7

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Cited by year (2026 to 13 Oct)

Citing papers per year: 2026: 1.

1 paper.

  1. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
  2. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  3. 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis
  4. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation
  5. 2026LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation
  6. 2025Understanding and Mitigating Errors of LLM-Generated RTL Code
  7. 2026Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair
  8. 2026Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes