mlsanityData to 7 Oct 2026

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

arXiv 2504.09485 ↗First posted 13 Apr 2025cs.LG cs.ARcited by 1

On the map: LLM reasoning → Reasoning benchmarks and evaluation

Abstract (arXiv)

The success of foundation AI has motivated the research of circuit foundation models, which are customized to assist the integrated circuit (IC) design process. However, existing pre-trained circuit foundation models are typically limited to standalone encoders for predictive tasks or decoders for generative tasks. These two model types are developed independently, operate on different circuit modalities, and reside in separate latent spaces. This restricts their ability to complement each other for more advanced capabilities. In this work, we present GenEDA, the first framework that cross-modally aligns circuit encoders with decoders within a shared latent space. GenEDA bridges the gap between graph-based circuit representation learning and text-based large language models (LLMs), enabling communication between their respective latent spaces. To achieve the alignment, we propose two paradigms to support both open-source trainable LLMs and commercial frozen LLMs. We leverage this aligned architecture to develop the first generative foundation model for netlists, unleashing LLMs' generative reasoning capability on the low-level and bit-blasted netlists. GenEDA enables three unprecedented generative netlist functional reasoning tasks, where it reversely generates high-level functionalities such as specifications and RTL code from low-level netlists. These tasks move beyond traditional gate function classification to direct generation of full-circuit functionality. Experiments demonstrate that GenEDA significantly boosts advanced LLMs' (e.g., GPT and DeepSeek series) performance in all tasks.

Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Placed in Reasoning benchmarks and evaluation, one of 17 directions in LLM reasoning. Builds on 28 of its 50 references that are in the map. First posted on arXiv 13 Apr 2025.

Builds on

28 of 50 references.

References · 28

  1. 2023Visual Instruction Tuningcited by 7,792
  2. 2023BLIP-2: Bootstrapping Language-Image Pre-training with Frozen Image Encoders and Large Language Modelscited by 6,069
  3. 2022BLIP: Bootstrapping Language-Image Pre-training for Unified Vision-Language Understanding and Generationcited by 4,310
  4. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
  5. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  6. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  7. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  8. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  9. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  10. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  11. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  12. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
16 more
  1. 2021DeepGate: Learning Neural Representations of Logic Gatescited by 37
  2. 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
  3. 2023(Security) Assertions by Large Language Modelscited by 31
  4. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 30
  5. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  6. 2023Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networkscited by 27
  7. 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
  8. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  9. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  10. 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
  11. 2024The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Modelscited by 12
  12. 2024FabGPT: An Efficient Large Multimodal Model for Complex Wafer Defect Knowledge Queriescited by 12
  13. 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
  14. 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
  15. 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representationscited by 5
  16. 2021ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineeringcited by 3

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Cited by year

Citing papers per year: 2025: 1.

1 paper.

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  1. 2026CircuitSynth: Reliable Synthetic Data Generation
  2. 2026AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval
  3. 2026Differentiable Faithfulness Alignment for Cross-Model Circuit Transfer
  4. 2024CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence
  5. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs
  6. 2023GENOME: GenerativE Neuro-symbOlic visual reasoning by growing and reusing ModulEs
  7. 2025Encode, Think, Decode: Scaling test-time reasoning with recursive latent thoughts
  8. 2026CircuitProbe: Predicting Reasoning Circuits in Transformers via Stability Zone Detection