mlsanityData to 14 Oct 2026

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

arXiv 2509.00071 ↗First posted 26 Aug 2025cs.LG cs.AIcited by 0

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Abstract (arXiv)

In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, we make the first attempt, SynCircuit, to generate new synthetic circuits with valid functionalities in the HDL format. SynCircuit automatically generates synthetic data using a framework with three innovative steps: 1) We propose a customized diffusion-based generative model to resolve the Directed Cyclic Graph (DCG) generation task, which has not been well explored in the AI community. 2) To ensure our circuit is valid, we enforce the circuit constraints by refining the initial graph generation outputs. 3) The Monte Carlo tree search (MCTS) method further optimizes the logic redundancy in the generated graph. Experimental results demonstrate that our proposed SynCircuit can generate more realistic synthetic circuits and enhance ML model performance in downstream circuit design tasks.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 23 of its 36 references that are in the map. First posted on arXiv 26 Aug 2025.

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23 of 36 references.

References · 23

  1. 2021Improved Denoising Diffusion Probabilistic Modelscited by 3,761
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  10. 2019D-VAE: A Variational Autoencoder for Directed Acyclic Graphscited by 98
  11. 2023Efficient and Degree-Guided Graph Generation via Discrete Diffusion Modelingcited by 80
  12. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
11 more
  1. 2020Efficient Nonmyopic Bayesian Optimization via One-Shot Multi-Step Treescited by 41
  2. 2024LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuitscited by 33
  3. 2019Gravity-Inspired Graph Autoencoders for Directed Link Predictioncited by 28
  4. 2023Sparse Training of Discrete Diffusion Models for Graph Generationcited by 27
  5. 2023MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Designcited by 19
  6. 2023GraphMaker: Can Diffusion Models Generate Large Attributed Graphs?cited by 18
  7. 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
  8. 2024Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesiscited by 10
  9. 2022Graph Generative Model for Benchmarking Graph Neural Networkscited by 6
  10. 2024Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimizationcited by 6
  11. 2023Circuit as Set of Pointscited by 3

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  1. 2024GraCo -- A Graph Composer for Integrated Circuits
  2. 2023Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation
  3. 2024SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation
  4. 2025AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation
  5. 2024ShortCircuit: AlphaZero-Driven Circuit Design
  6. 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models
  7. 2025CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
  8. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation