mlsanityData to 14 Oct 2026

Understanding and Mitigating Errors of LLM-Generated RTL Code

arXiv 2508.05266 ↗First posted 7 Aug 2025cs.AR cs.CL cs.LGcited by 8

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Abstract (arXiv)

Despite limited success in large language model (LLM)-based register-transfer-level (RTL) code generation, the root causes of errors remain poorly understood. To address this, we conduct a comprehensive error analysis, finding that most failures arise not from deficient reasoning, but from a lack of RTL programming knowledge, insufficient circuit understanding, ambiguous specifications, or misinterpreted multimodal inputs. Leveraging in-context learning, we propose targeted correction techniques: a retrieval-augmented generation (RAG) knowledge base to supply domain expertise; design description rules with rule-checking to clarify inputs; external tools to convert multimodal data into LLM-compatible formats; and an iterative simulation-debugging loop for remaining errors. Integrating these into an LLM-based framework yields significant improvement, achieving 98.1% accuracy on the VerilogEval benchmark with DeepSeek-v3.2-Speciale, demonstrating the effectiveness of our approach.

Key facts. Cited by 8 papers in the map (data through 14 Oct 2026). Builds on 27 of its 43 references that are in the map. First posted on arXiv 7 Aug 2025.

Builds on

27 of 43 references.

References · 27

  1. 2023GPT-4 Technical Reportcited by 18,396
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2024Qwen2.5-Coder Technical Reportcited by 1,203
  4. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 885
  5. 2023A Comprehensive Overview of Large Language Modelscited by 648
  6. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  7. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  8. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  9. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  10. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  11. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  12. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
15 more
  1. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  2. 2020DAVE: Deriving Automatically Verilog from Englishcited by 48
  3. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  4. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  5. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 35
  6. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
  7. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  8. 2024HLSPilot: LLM-based High-Level Synthesiscited by 25
  9. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  10. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  11. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  12. 2025VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correctioncited by 12
  13. 2025VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistencycited by 11
  14. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  15. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 2; 2026: 6.

8 papers.

  1. 2025An Empirical Study on Failures in Automated Issue Solvingcited by 16
  2. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  3. 2026UCAgent: An End-to-End Agent for Block-Level Functional Verificationcited by 2
  4. 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMscited by 2
  5. 2026LEGO: An LLM Skill-Based Front-End Design Generation Platformcited by 0
  6. 2026EstRTL: Functional Estimation Guided RTL Code Generationcited by 0
  7. 2026How LLMs Fail and Generalize in RTL Coding for Hardware Design?cited by 0
  8. 2026SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specificationscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  2. 2024EDA-Aware RTL Generation with Large Language Models
  3. 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis
  4. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
  5. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
  6. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
  7. 2026LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation
  8. 2025Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware