RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts

arXiv 2503.21971 ↗First posted 27 Mar 2025cs.LG cs.SEcited by 0

On the map: Mixture-of-experts → Mixture of LoRA experts

Abstract (arXiv)

This paper presents RocketPPA, a novel ultra-fast power, performance (delay), and area (PPA) estimator operating directly at the code-level abstraction using HDL code as input. The key technical innovation is its LLM-based regression model, which uniquely integrates a large language model (LLM) with a mixture-of-experts (MoE) architecture composed of multilayer perceptrons (MLPs). The LLM interprets the input HDL code and then utilizes its final hidden-layer representations to predict PPA metrics. Low-rank adaptation (LoRA) is used for parameter-efficient fine-tuning to enable efficient LLM training. Furthermore, the work includes the development of an LLM-based HDL code repair framework to generate a large and synthesizable training dataset. Experimental results on the VerilogEval benchmark demonstrate that RocketPPA achieves significant improvements in the accuracy of PPA estimation compared to previous state-of-the-art methods like Llama3-MetRex-8B. Specifically, at a 10% relative error threshold, RocketPPA enhances the pass rate for area prediction by 13.6%, delay by 9.4%, and power by 14.7%. At a 20% threshold, the improvements are 9.6% for area, 10.8% for delay, and 18.5% for power. Moreover, RocketPPA achieves a speedup of over 20x compared to MetRex and 30x over MasterRTL in processing the test set. The impact of RocketPPA is the potential to substantially accelerate the hardware design process by providing accurate PPA estimations early in the design cycle, thus avoiding the overhead of manual feature engineering and time-consuming synthesis flows.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Placed in Mixture of LoRA experts, one of 12 directions in Mixture-of-experts. Builds on 20 of its 27 references that are in the map. First posted on arXiv 27 Mar 2025.

Builds on

20 of 27 references.

References · 20

2024The Llama 3 Herd of Modelscited by 14,192
2020Longformer: The Long-Document Transformercited by 3,362
2023Code Llama: Open Foundation Models for Codecited by 2,105
2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 24
2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23

8 more

2023MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Designcited by 19
2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
2025LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Modelscited by 7
2025RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Frameworkcited by 3

Built on by

Not cited yet.

Similar, not cited

Close in wording, no citation either way