Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
On the map: LLM agents and tool use → Software engineering coding agents
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Abstract (arXiv)
Recent advances in large language models (LLMs) have sparked growing interest in automatic RTL optimization for better performance, power, and area (PPA). However, existing methods are still far from realistic RTL optimization. Their evaluation settings are often unrealistic: they are tested on manually degraded, small-scale RTL designs and rely on weak open-source tools. Their optimization methods are also limited, relying on coarse design-level feedback and simple pre-defined rewriting rules. To address these limitations, we present Dr. RTL, an agentic framework for RTL timing optimization in a realistic evaluation environment, with continual self-improvement through reusable optimization skills. We establish a realistic evaluation setting with more challenging RTL designs and an industrial EDA workflow. Within this setting, Dr. RTL performs closed-loop optimization through a multi-agent framework for critical-path analysis, parallel RTL rewriting, and tool-based evaluation. We further introduce group-relative skill learning, which compares parallel RTL rewrites and distills the optimization experience into an interpretable skill library. Currently, this library contains 47 pattern--strategy entries for cross-design reuse to improve PPA and accelerate convergence, and it can continue evolving over time. Evaluated on 20 real-world RTL designs, Dr. RTL achieves average WNS/TNS improvements of 21%/17% with a 6% area reduction over the industry-leading commercial synthesis tool.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 22 of its 41 references that are in the map. First posted on arXiv 16 Apr 2026.
Builds on
22 of 41 references.
Closest ancestors · 3
Same direction, newest first
- 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization17 Mar
- 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs10 Feb
- 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation10 Dec
Other references · 19
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
- 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
- 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
- 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
- 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
- 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
- 2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 18
- 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
- 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
- 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
- 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
- 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimizationcited by 11
7 more
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2024E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesiscited by 7
- 2025The Dawn of Agentic EDA: A Survey of Autonomous Digital Chip Designcited by 7
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
- 2026RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learningcited by 4
- 2025BoolE: Exact Symbolic Reasoning via Boolean Equality Saturationcited by 3
- 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosiscited by 1
Built on by
Citing papers per year: 2026: 6.
6 papers.
- 2026ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agentscited by 1
- 2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generationcited by 0
- 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedbackcited by 0
- 2026ChipMEM: Verification-Grounded Memory for EDA Agentscited by 0
- 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0
- 2026LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisationcited by 0
- 2026LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation12 Oct 2026
- 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification28 Sep 2026
- 2026ChipMEM: Verification-Grounded Memory for EDA Agents22 Sep 2026
- 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback9 Aug 2026
- 2026ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents30 Jul 2026
- 2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation26 May 2026
Similar, not cited
Close in wording, no citation either way
- 2026Alpha-RTL: Test-Time Training for RTL Hardware Optimization
- 2026RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
- 2025Automated Multi-Agent Workflows for RTL Design
- 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI
- 2026ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation
- 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
- 2026Can Agents Design Better Chips with a Higher Level Abstraction?