TuRTLe: A Unified Evaluation of LLMs for RTL Generation
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Abstract (arXiv)
The rapid advancements in LLMs have driven the adoption of generative AI in various domains, including Electronic Design Automation (EDA). Unlike traditional software development, EDA presents unique challenges, as generated RTL code must not only be syntactically correct and functionally accurate but also synthesizable by hardware generators while meeting performance, power, and area constraints. These additional requirements introduce complexities that existing code-generation benchmarks often fail to capture, limiting their effectiveness in evaluating LLMs for RTL generation. To address this gap, we propose TuRTLe, a unified evaluation framework designed to systematically assess LLMs across key RTL generation tasks. TuRTLe integrates multiple existing benchmarks and automates the evaluation process, enabling a comprehensive assessment of LLM performance in syntax correctness, functional correctness, synthesis, PPA optimization, and exact line completion. Using this framework, we benchmark a diverse set of open LLMs and analyze their strengths and weaknesses in EDA-specific tasks. Our results show that reasoning-based models, such as DeepSeek R1, consistently outperform others across multiple evaluation criteria, but at the cost of increased computational overhead and inference latency. Additionally, base models are better suited in module completion tasks, while instruct-tuned models perform better in specification-to-RTL tasks.
Key facts. Cited by 9 papers in the map (data through 14 Oct 2026). Builds on 41 of its 58 references that are in the map. First posted on arXiv 31 Mar 2025.
Builds on
41 of 58 references.
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29 more
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Built on by
Citing papers per year: 2025: 3; 2026: 6.
9 papers.
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generationcited by 4
- 2025Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Codecited by 3
- 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimizationcited by 2
- 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocolscited by 1
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 1
- 2026LEGO: An LLM Skill-Based Front-End Design Generation Platformcited by 0
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generationcited by 0
- 2026VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generationcited by 0
- 2026VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation4 Oct 2026
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration27 Aug 2026
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generation30 Apr 2026
- 2026LEGO: An LLM Skill-Based Front-End Design Generation Platform25 Apr 2026
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation18 Apr 2026
- 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization17 Mar 2026
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generation23 Dec 2025
- 2025Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code16 Oct 2025
- 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols9 Jun 2025
Similar, not cited
Close in wording, no citation either way
- 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
- 2024EDA-Aware RTL Generation with Large Language Models
- 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
- 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI
- 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
- 2026Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
- 2025Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware
- 2026StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis