mlsanityData to 7 Oct 2026

LLM4RTL: Tool-Assisted LLM for RTL Generation

arXiv 2606.15500 ↗First posted 13 Jun 2026cs.AR cs.AI cs.SYcited by 0

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Abstract (arXiv)

Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems. Concurrently, a significant body of research has developed which explores a growing variety of methods and systems for applying LLMs to hardware and chip design (e.g., systems for RTL code generation based on functional description). However, when it comes to open Verilog/RTL code-generation, we need high-quality training samples to build specialized and more effective LLM systems through fine-tuning or low-rank adaptation. Here, we propose a ``judge-renew-check-renew-check'' (JRCRC) pipeline which updates a current public dataset using a hierarchy of state-of-the-art commercial LLM models differing in their costs and capabilities in RTL code generation. This approach achieves a cost-effective mechanism for filtering and refining code-generation samples into a higher-quality training dataset. Our experiments also identify some common weaknesses of LLMs in rule-based reasoning and logic, and consequently, in RTL code-generation. Having identified these weaknesses, we develop an architecture for incorporating pre-processing tools to dynamically assist the LLMs in inferring logical relationships from tabular data formats. With our tools-assisted architecture for RTL code generation, we achieve significant overall performance gains in the VerilogEval benchmark and outperform many state-of-the-art methods. Our LLM4RTL system achieves performance comparable to that of GPT-4O using a significantly much smaller LLM.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 12 of its 19 references that are in the map. First posted on arXiv 13 Jun 2026.

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12 of 19 references.

References · 12

  1. 2020Language Models are Few-Shot Learnerscited by 32,199
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  3. 2021AMMUS : A Survey of Transformer-based Pretrained Models in Natural Language Processingcited by 131
  4. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  5. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  6. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  7. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  8. 2024Inductive or Deductive? Rethinking the Fundamental Reasoning Abilities of LLMscited by 29
  9. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 24
  10. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  11. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  12. 2025How well do LLMs reason over tabular data, really?cited by 6

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  1. 2025Understanding and Mitigating Errors of LLM-Generated RTL Code
  2. 2026LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation
  3. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation
  4. 2024EDA-Aware RTL Generation with Large Language Models
  5. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
  6. 2025Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
  7. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  8. 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis