Data to 14 Oct 2026

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

arXiv 2407.18333 ↗First posted 21 Jul 2024cs.AR cs.AIcited by 36

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Abstract (arXiv)

Recently, the use of large language models (LLMs) for software code generation, e.g., C/C++ and Python, has proven a great success. However, LLMs still suffer from low syntactic and functional correctness when it comes to the generation of register-transfer level (RTL) code, such as Verilog. To address this issue, in this paper, we develop AutoVCoder, a systematic open-source framework that significantly improves the LLMs' correctness of generating Verilog code and enhances the quality of its output at the same time. Our framework integrates three novel techniques, including a high-quality hardware dataset generation approach, a two-round LLM fine-tuning method and a domain-specific retrieval-augmented generation (RAG) mechanism. Experimental results demonstrate that AutoVCoder outperforms both industrial and academic LLMs in Verilog code generation. Specifically, AutoVCoder shows a 0.5% and 2.2% improvement in functional correctness on the EvalMachine and EvalHuman benchmarks compared with BetterV, and also achieves a 3.4% increase in syntax correctness and a 3.4% increase in functional correctness on the RTLLM benchmark compared with RTLCoder.

Key facts. Cited by 36 papers in the map (data through 14 Oct 2026). Builds on 25 of its 26 references that are in the map. First posted on arXiv 21 Jul 2024.

Builds on

25 of 26 references.

References · 25

2023GPT-4 Technical Reportcited by 18,396
2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,380
2021Evaluating Large Language Models Trained on Codecited by 8,320
2018Representation Learning with Contrastive Predictive Codingcited by 7,777
2023Qwen Technical Reportcited by 3,344
2023Code Llama: Open Foundation Models for Codecited by 2,139
2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,181
2021CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generationcited by 906
2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 885
2023StarCoder: may the source be with you!cited by 799
2022InCoder: A Generative Model for Code Infilling and Synthesiscited by 498
2023TinyStories: How Small Can Language Models Be and Still Speak Coherent English?cited by 449

13 more

2023CodeGeeX: A Pre-Trained Model for Code Generation with Multilingual Benchmarking on HumanEval-Xcited by 300
2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
2023CodeGen2: Lessons for Training LLMs on Programming and Natural Languagescited by 125
2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
2023ChipGPT: How far are we from natural language hardware designcited by 105
2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
2023A Multi-Task Embedder For Retrieval Augmented LLMscited by 64
2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 2; 2025: 21; 2026: 13.

36 papers.

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2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8

24 more

2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 6
2025ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awarenesscited by 5
2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Promptscited by 2
2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generationcited by 2
2025HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databasescited by 1
2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
2025QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Designcited by 1
2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generationcited by 1
2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Languagecited by 0
2025VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learningcited by 0
2026IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolutioncited by 0
2026LEGO: An LLM Skill-Based Front-End Design Generation Platformcited by 0
2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generationcited by 0
2026ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewardscited by 0
2026EstRTL: Functional Estimation Guided RTL Code Generationcited by 0
2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
2026Benchmarking LLMs for Verilog Design Flowscited by 0

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