mlsanityData to 7 Oct 2026

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog

arXiv 2409.15186 ↗First posted 23 Sep 2024cs.AR cs.AIcited by 8

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Abstract (arXiv)

Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their strong programming capabilities. However, no work has yet considered using LLMs for bug localization in Verilog code. This paper presents Location-is-Key, an opensource LLM solution to locate functional errors in Verilog snippets. LiK achieves high localization accuracy, with a pass@1 localization accuracy of 93.3% on our test dataset based on RTLLM, surpassing GPT-4's 77.9% and comparable to Claude-3.5's 90.8%. Additionally, the bug location obtained by LiK significantly improves GPT-3.5's bug repair efficiency (Functional pass@1 increased from 40.39% to 58.92%), highlighting the importance of bug localization in LLM-based Verilog debugging. Compared to existing methods, LiK only requires the design specification and the erroneous code snippet, without the need for testbenches, assertions, or any other EDA tools. This research demonstrates the feasibility of using LLMs for Verilog error localization, thus providing a new direction for automatic Verilog code debugging.

Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). Builds on 19 of its 36 references that are in the map. First posted on arXiv 23 Sep 2024.

Builds on

19 of 36 references.

References · 19

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,084
  2. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,302
  3. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  4. 2022Training a Helpful and Harmless Assistant with Reinforcement Learning from Human Feedbackcited by 3,634
  5. 2024SimPO: Simple Preference Optimization with a Reference-Free Rewardcited by 951
  6. 2019CodeSearchNet Challenge: Evaluating the State of Semantic Code Searchcited by 638
  7. 2024DeepSeek-Coder-V2: Breaking the Barrier of Closed-Source Models in Code Intelligencecited by 325
  8. 2019Devign: Effective Vulnerability Identification by Learning Comprehensive Program Semantics via Graph Neural Networkscited by 266
  9. 2023Software Testing with Large Language Models: Survey, Landscape, and Visioncited by 163
  10. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  11. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  12. 2021Examining Zero-Shot Vulnerability Repair with Large Language Modelscited by 105
7 more
  1. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  2. 2023Large Language Models for Test-Free Fault Localizationcited by 67
  3. 2024A Deep Dive into Large Language Models for Automated Bug Localization and Repaircited by 39
  4. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  5. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  6. 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledgecited by 10
  7. 2024VeriBug: An Attention-based Framework for Bug-Localization in Hardware Designscited by 3

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 5; 2026: 3.

8 papers.

  1. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 8
  2. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 6
  3. 2026ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMscited by 5
  4. 2025A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extractioncited by 3
  5. 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specificationscited by 3
  6. 2025R3A: Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generationcited by 1
  7. 2026TOPCELL: Topology Optimization of Standard Cell via LLMscited by 0
  8. 2026Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repaircited by 0