mlsanityData to 7 Oct 2026

AutoChip: Automating HDL Generation Using LLM Feedback

arXiv 2311.04887 ↗First posted 8 Nov 2023cs.PLcited by 80

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Abstract (arXiv)

Traditionally, designs are written in Verilog hardware description language (HDL) and debugged by hardware engineers. While this approach is effective, it is time-consuming and error-prone for complex designs. Large language models (LLMs) are promising in automating HDL code generation. LLMs are trained on massive datasets of text and code, and they can learn to generate code that compiles and is functionally accurate. We aim to evaluate the ability of LLMs to generate functionally correct HDL models. We build AutoChip by combining the interactive capabilities of LLMs and the output from Verilog simulations to generate Verilog modules. We start with a design prompt for a module and the context from compilation errors and debugging messages, which highlight differences between the expected and actual outputs. This ensures that accurate Verilog code can be generated without human intervention. We evaluate AutoChip using problem sets from HDLBits. We conduct a comprehensive analysis of the AutoChip using several LLMs and problem categories. The results show that incorporating context from compiler tools, such as Icarus Verilog, improves the effectiveness, yielding 24.20% more accurate Verilog. We release our evaluation scripts and datasets as open-source contributions at the following link https://github.com/shailja-thakur/AutoChip.

Key facts. Cited by 80 papers in the map (data through 7 Oct 2026). First posted on arXiv 8 Nov 2023.

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 1; 2024: 20; 2025: 39; 2026: 20.

80 papers.

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  1. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  2. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  3. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
  4. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  5. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  6. 2024PropertyGPT: LLM-driven Formal Verification of Smart Contracts through Retrieval-Augmented Property Generationcited by 36
  7. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  8. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
  9. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  10. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  11. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
  12. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
38 more
  1. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  2. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  3. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  4. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 16
  5. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  6. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 14
  7. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  8. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 12
  9. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  10. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  11. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  12. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  13. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  14. 2025Can Reasoning Models Reason about Hardware? An Agentic HLS Perspectivecited by 9
  15. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  16. 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
  17. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  18. 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
  19. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentationcited by 7
  20. 2025Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlistscited by 7
  21. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  22. 2025BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesiscited by 6
  23. 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
  24. 2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6
  25. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
  26. 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
  27. 2025Using GUI Agent for Electronic Design Automationcited by 5
  28. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  29. 2024Classification-Based Automatic HDL Code Generation Using LLMscited by 3
  30. 2025RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Frameworkcited by 3
  31. 2025CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Referencecited by 3
  32. 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
  33. 2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2
  34. 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
  35. 2025Evaluating LLM-based Workflows for Switched-Mode Power Supply Designcited by 2
  36. 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Codecited by 2
  37. 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimizationcited by 2
  38. 2024Digital ASIC Design with Ongoing LLMs: Strategies and Prospectscited by 1

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