Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques
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Abstract (arXiv)
Large Language Models (LLMs) have attracted considerable attention in recent years due to their remarkable compatibility with Hardware Description Language (HDL) design. In this paper, we examine the performance of three major LLMs, Claude 3 Opus, ChatGPT-4, and ChatGPT-4o, in designing finite state machines (FSMs). By utilizing the instructional content provided by HDLBits, we evaluate the stability, limitations, and potential approaches for improving the success rates of these models. Furthermore, we explore the impact of using the prompt-refining method, To-do-Oriented Prompting (TOP) Patch, on the success rate of these LLM models in various FSM design scenarios. The results show that the systematic format prompt method and the novel prompt refinement method have the potential to be applied to other domains beyond HDL design automation, considering its possible integration with other prompt engineering techniques in the future.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 5 of its 6 references that are in the map. First posted on arXiv 26 Mar 2025.
Builds on
5 of 6 references.
References · 5
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
- 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
- 2020DAVE: Deriving Automatically Verilog from Englishcited by 48
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Citing papers per year: 2026: 1.
1 paper.