GUIDE: GenAI Units In Digital Design Education
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Abstract (arXiv)
GenAI Units In Digital Design Education (GUIDE) is an open courseware repository with runnable Google Colab labs and other materials. We describe the repository's architecture and educational approach based on standardized teaching units comprising slides, short videos, runnable labs, and related papers. This organization enables consistency for both the students' learning experience and the reuse and grading by instructors. We demonstrate GUIDE in practice with three representative units: VeriThoughts for reasoning and formal-verification-backed RTL generation, enhanced LLM-aided testbench generation, and LLMPirate for IP Piracy. We also provide details for four example course instances (GUIDE4ChipDesign, Build your ASIC, GUIDE4HardwareSecurity, and Hardware Design) that assemble GUIDE units into full semester offerings, learning outcomes, and capstone projects, all based on proven materials. For example, the GUIDE4HardwareSecurity course includes a project on LLM-aided hardware Trojan insertion that has been successfully deployed in the classroom and in Cybersecurity Games and Conference (CSAW), a student competition and academic conference for cybersecurity. We also organized an NYU Cognichip Hackathon, engaging students across 24 international teams in AI-assisted RTL design workflows. The GUIDE repository is open for contributions and available at: https://github.com/FCHXWH823/LLM4ChipDesign.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 24 of its 31 references that are in the map. First posted on arXiv 18 Mar 2026.
Builds on
24 of 31 references.
References · 24
- 2017Attention Is All You Needcited by 59,932
- 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
- 2023(Security) Assertions by Large Language Modelscited by 31
- 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
- 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
- 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
- 2024LLM-Aided Testbench Generation and Bug Detection for Finite-State Machinescited by 15
- 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
- 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 13
- 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
- 2022ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learningcited by 11
12 more
- 2024LLM-Aided Efficient Hardware Design Automationcited by 11
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
- 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
- 2024LLMPirate: LLMs for Black-box Hardware IP Piracycited by 7
- 2025Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Formcited by 7
- 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVAcited by 5
- 2025LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMscited by 5
- 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
- 2025TrojanLoC: LLM-based Framework for RTL Trojan Localizationcited by 5
- 2024PrefixLLM: LLM-aided Prefix Circuit Designcited by 3
- 2024Unleashing GHOST: An LLM-Powered Framework for Automated Hardware Trojan Designcited by 2
- 2024Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learningcited by 1
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