EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD
Not on the map. Why?
Abstract (arXiv)
Large language models (LLMs) serve as powerful tools for design, providing capabilities for both task automation and design assistance. Recent advancements have shown tremendous potential for facilitating LLM integration into the chip design process; however, many of these works rely on data that are not publicly available and/or not permissively licensed for use in LLM training and distribution. In this paper, we present a solution aimed at bridging this gap by introducing an open-source dataset tailored for OpenROAD, a widely adopted open-source EDA toolchain. The dataset features over 1000 data points and is structured in two formats: (i) a pairwise set comprised of question prompts with prose answers, and (ii) a pairwise set comprised of code prompts and their corresponding OpenROAD scripts. By providing this dataset, we aim to facilitate LLM-focused research within the EDA domain. The dataset is available at https://github.com/OpenROAD-Assistant/EDA-Corpus.
Key facts. Cited by 13 papers in the map (data through 14 Oct 2026). Builds on 12 of its 27 references that are in the map. First posted on arXiv 4 May 2024.
Builds on
12 of 27 references.
References · 12
- 2023LIMA: Less Is More for Alignmentcited by 1,100
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
- 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
- 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
- 2023ChipGPT: How far are we from natural language hardware designcited by 105
- 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
- 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
- 2023Unlocking Hardware Security Assurance: The Potential of LLMscited by 9
- 2023iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Librarycited by 7
Built on by
Citing papers per year: 2024: 2; 2025: 8; 2026: 3.
13 papers.
Sort:
By area:
- 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
- 2024ORAssistant: A Custom RAG-based Conversational Assistant for OpenROADcited by 4
- 2025Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graphcited by 3
- 2026Automated QoR improvement in OpenROAD with coding agentscited by 3
- 2025Improving LLM-Powered EDA Assistants with RAFTcited by 2
- 2024ALKAFI-LLAMA3: Fine-Tuning LLMs for Precise Legal Understanding in Palestinecited by 1
- 2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Languagecited by 0
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Designcited by 0
- 2026SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specificationscited by 0
1 more
- 2026LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation12 Oct 2026
- 2026SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specifications27 Sep 2026
- 2026Automated QoR improvement in OpenROAD with coding agents9 Jan 2026
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs20 Jul 2025
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design13 Jul 2025
- 2025Improving LLM-Powered EDA Assistants with RAFT6 Jun 2025
- 2025Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph15 Apr 2025
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset11 Mar 2025
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis25 Feb 2025
- 2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language14 Feb 2025
- 2025A Survey of Research in Large Language Models for Electronic Design Automation16 Jan 2025
- 2024ALKAFI-LLAMA3: Fine-Tuning LLMs for Precise Legal Understanding in Palestine19 Dec 2024
1 more
- 2026Automated QoR improvement in OpenROAD with coding agentscited by 3
- 2026Automated QoR improvement in OpenROAD with coding agents9 Jan 2026
- 2025Improving LLM-Powered EDA Assistants with RAFTcited by 2
- 2025Improving LLM-Powered EDA Assistants with RAFT6 Jun 2025
- 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
- 2024ORAssistant: A Custom RAG-based Conversational Assistant for OpenROADcited by 4
- 2025Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graphcited by 3
- 2024ALKAFI-LLAMA3: Fine-Tuning LLMs for Precise Legal Understanding in Palestinecited by 1
- 2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Languagecited by 0
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Designcited by 0
- 2026SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specificationscited by 0
- 2026LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisationcited by 0
- 2026LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation12 Oct 2026
- 2026SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specifications27 Sep 2026
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design13 Jul 2025
- 2025Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph15 Apr 2025
- 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset11 Mar 2025
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis25 Feb 2025
- 2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language14 Feb 2025
- 2025A Survey of Research in Large Language Models for Electronic Design Automation16 Jan 2025
- 2024ALKAFI-LLAMA3: Fine-Tuning LLMs for Precise Legal Understanding in Palestine19 Dec 2024
- 2024ORAssistant: A Custom RAG-based Conversational Assistant for OpenROAD4 Oct 2024