mlsanityData to 7 Oct 2026

DUET: Agentic Design Understanding via Experimentation and Testing

arXiv 2512.06247 ↗First posted 6 Dec 2025cs.SE cs.AI cs.ARcited by 0

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

AI agents powered by large language models (LLMs) are being used to solve increasingly complex software engineering challenges, but struggle with hardware design tasks. Register Transfer Level (RTL) code presents a unique challenge for LLMs, as it encodes complex, dynamic, time-evolving behaviors using the low-level language features of SystemVerilog. LLMs struggle to infer these complex behaviors from the syntax of RTL alone, which limits their ability to complete all downstream tasks like code completion, documentation, or verification. In response to this issue, we present DUET: a general methodology for developing Design Understanding via Experimentation and Testing. DUET mimics how hardware design experts develop an understanding of complex designs: not just via a one-off readthrough of the RTL, but via iterative experimentation using a number of tools. DUET iteratively generates hypotheses, tests them with EDA tools (e.g., simulation, waveform inspection, and formal verification), and integrates the results to build a bottom-up understanding of the design. In our evaluations, we show that DUET improves AI agent performance on formal verification, when compared to a baseline flow without experimentation.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 25 of its 35 references that are in the map. First posted on arXiv 6 Dec 2025.

Builds on

25 of 35 references.

Closest ancestors · 2

Same direction, newest first

  1. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool15 Aug
  2. 2023ChatDev: Communicative Agents for Software Development16 Jul

Other references · 23

  1. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  2. 2023An Empirical Evaluation of Using Large Language Models for Automated Unit Test Generationcited by 193
  3. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  4. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  5. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  6. 2023ChatUniTest: A Framework for LLM-Based Test Generationcited by 94
  7. 2023No More Manual Tests? Evaluating and Improving ChatGPT for Unit Test Generationcited by 82
  8. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  9. 2023Effective Test Generation Using Pre-trained Large Language Models and Mutation Testingcited by 51
  10. 2025Co-Evolving LLM Coder and Unit Tester via Reinforcement Learningcited by 51
  11. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  12. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
11 more
  1. 2024HITS: High-coverage LLM-based Unit Test Generation via Method Slicingcited by 37
  2. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  3. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  4. 2023Reinforcement Learning from Automatic Feedback for High-Quality Unit Test Generationcited by 21
  5. 2024TestART: Improving LLM-based Unit Testing via Co-evolution of Automated Generation and Repair Iterationcited by 20
  6. 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
  7. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 16
  8. 2024AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generationcited by 16
  9. 2024ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generationcited by 15
  10. 2024TestSpark: IntelliJ IDEA's Ultimate Test Generation Companioncited by 9
  11. 2024LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verificationcited by 6

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  1. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
  2. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
  3. 2026Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
  4. 2025ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
  5. 2026AgentDV: Closed-Loop Agentic AI for Hardware Design Verification
  6. 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
  7. 2025RTLSquad: Multi-Agent Based Interpretable RTL Design
  8. 2026CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents