mlsanityData to 7 Oct 2026

AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design

arXiv 2512.21613 ↗First posted 25 Dec 2025cs.AIcited by 0

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

In this paper, we propose AMS-IO-Agent, a domain-specialized LLM-based agent for structure-aware input/output (I/O) subsystem generation in analog and mixed-signal (AMS) integrated circuits (ICs). The central contribution of this work is a framework that connects natural language design intent with industrial-level AMS IC design deliverables. AMS-IO-Agent integrates two key capabilities: (1) a structured domain knowledge base that captures reusable constraints and design conventions; (2) design intent structuring, which converts ambiguous user intent into verifiable logic steps using JSON and Python as intermediate formats. We further introduce AMS-IO-Bench, a benchmark for wirebond-packaged AMS I/O ring automation. On this benchmark, AMS-IO-Agent achieves over 70% DRC+LVS pass rate and reduces design turnaround time from hours to minutes, outperforming the baseline LLM. Furthermore, an agent-generated I/O ring was fabricated and validated in a 28 nm CMOS tape-out, demonstrating the practical effectiveness of the approach in real AMS IC design flows. To our knowledge, this is the first reported human-agent collaborative AMS IC design in which an LLM-based agent completes a nontrivial subtask with outputs directly used in silicon.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 13 of its 20 references that are in the map. First posted on arXiv 25 Dec 2025.

Builds on

13 of 20 references.

Closest ancestors · 2

Same direction, newest first

  1. 2025ORFS-agent: Tool-Using Agents for Chip Design Optimization10 Jun
  2. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDA20 Aug

Other references · 11

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  3. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  4. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  5. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  6. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  7. 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
  8. 2024Ask-EDA: A Design Assistant Empowered by LLM, Hybrid RAG and Abbreviation De-hallucinationcited by 14
  9. 2024LLM-Aided Efficient Hardware Design Automationcited by 11
  10. 2025CIRCUIT: A Benchmark for Circuit Interpretation and Reasoning Capabilities of LLMscited by 11
  11. 2024Large Language Model (LLM) for Standard Cell Layout Design Optimizationcited by 9

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  1. 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization
  2. 2024AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG
  3. 2026RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
  4. 2025White-Box Reasoning: Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design
  5. 2026AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents
  6. 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits
  7. 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
  8. 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks