mlsanityData to 14 Oct 2026

VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation

arXiv 2510.27617 ↗First posted 31 Oct 2025cs.AIcited by 15

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

Automation of Register Transfer Level (RTL) design can help developers meet increasing computational demands. Large Language Models (LLMs) show promise for Hardware Description Language (HDL) generation, but face challenges due to limited parametric knowledge and domain-specific constraints. While prompt engineering and fine-tuning have limitations in knowledge coverage and training costs, multi-agent architectures offer a training-free paradigm to enhance reasoning through collaborative generation. However, current multi-agent approaches suffer from two critical deficiencies: susceptibility to noise propagation and constrained reasoning space exploration. We propose VeriMoA, a training-free mixture-of-agents (MoA) framework with two synergistic innovations. First, a quality-guided caching mechanism to maintain all intermediate HDL outputs and enables quality-based ranking and selection across the entire generation process, encouraging knowledge accumulation over layers of reasoning. Second, a multi-path generation strategy that leverages C++ and Python as intermediate representations, decomposing specification-to-HDL translation into two-stage processes that exploit LLM fluency in high-resource languages while promoting solution diversity. Comprehensive experiments on VerilogEval 2.0 and RTLLM 2.0 benchmarks demonstrate that VeriMoA achieves 15--30% improvements in Pass@1 across diverse LLM backbones, especially enabling smaller models to match larger models and fine-tuned alternatives without requiring costly training.

Key facts. Cited by 15 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 31 of its 43 references that are in the map. First posted on arXiv 31 Oct 2025.

Builds on

31 of 43 references.

Closest ancestors · 3

Same direction, newest first

  1. 2025Automated Multi-Agent Workflows for RTL Design24 Sep
  2. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation15 Dec
  3. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation10 Dec

Other references · 28

  1. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
  2. 2017Outrageously Large Neural Networks: The Sparsely-Gated Mixture-of-Experts Layercited by 3,509
  3. 2023Improving Factuality and Reasoning in Language Models through Multiagent Debatecited by 1,784
  4. 2023Encouraging Divergent Thinking in Large Language Models through Multi-Agent Debatecited by 1,011
  5. 2023LLM-Blender: Ensembling Large Language Models with Pairwise Ranking and Generative Fusioncited by 564
  6. 2024Mixture-of-Agents Enhances Large Language Model Capabilitiescited by 438
  7. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  8. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  9. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  10. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  11. 2025Rethinking Mixture-of-Agents: Is Mixing Different Large Language Models Beneficial?cited by 54
  12. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
16 more
  1. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  2. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  3. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  4. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 25
  5. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  6. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  7. 2024Automated C/C++ Program Repair for High-Level Synthesis via Large Language Modelscited by 18
  8. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  9. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  10. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  11. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  12. 2025Paradigm-Based Automatic HDL Code Generation Using LLMscited by 6
  13. 2025Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Designcited by 6
  14. 2025Network-informed Prompt Engineering against Organized Astroturf Campaigns under Extreme Class Imbalancecited by 4
  15. 2024Classification-Based Automatic HDL Code Generation Using LLMscited by 3
  16. 2025AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Codecited by 2

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 1; 2026: 14.

15 papers.

Sort:

By area:

Similar, not cited

Close in wording, no citation either way

  1. 2026ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
  2. 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
  3. 2024Enabling New HDLs with Agents
  4. 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
  5. 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
  6. 2025ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
  7. 2026Agentic Separation Logic Specification Synthesis
  8. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification