mlsanityData to 14 Oct 2026

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection

arXiv 2505.19734 ↗First posted 26 May 2025cs.AI cs.ARcited by 6

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Abstract (arXiv)

Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is increasing interest in applying LLMs to assist with HDL coding. Recent efforts have demonstrated the potential of LLMs in translating natural language to traditional HDL Verilog. Chisel, a next-generation HDL based on Scala, introduces higher-level abstractions, facilitating more concise, maintainable, and scalable hardware designs. However, the potential of using LLMs for Chisel code generation remains largely unexplored. This work proposes ReChisel, an LLM-based agentic system designed to enhance the effectiveness of Chisel code generation. ReChisel incorporates a reflection mechanism to iteratively refine the quality of generated code using feedback from compilation and simulation processes, and introduces an escape mechanism to break free from non-progress loops. Experiments demonstrate that ReChisel significantly improves the success rate of Chisel code generation, achieving performance comparable to state-of-the-art LLM-based agentic systems for Verilog code generation.

Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). Builds on 19 of its 37 references that are in the map. First posted on arXiv 26 May 2025.

Builds on

19 of 37 references.

References · 19

  1. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
  2. 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,695
  3. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  4. 2023Reflexion: Language Agents with Verbal Reinforcement Learningcited by 4,276
  5. 2022A Survey on In-context Learningcited by 721
  6. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  7. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  8. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  9. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  10. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  11. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  12. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
7 more
  1. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  2. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  3. 2020DAVE: Deriving Automatically Verilog from Englishcited by 48
  4. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  5. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  6. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  7. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 3; 2026: 3.

6 papers.

  1. 2025TokenPowerBench: Benchmarking the Power Consumption of LLM Inferencecited by 22
  2. 2025cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolutioncited by 7
  3. 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specificationscited by 4
  4. 2026RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generationcited by 1
  5. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
  6. 2026SparseCraft: Agentic Hardware-Software Co-Optimization for Sparse Computingcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  2. 2025Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
  3. 2025hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
  4. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
  5. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  6. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  7. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  8. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs