DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models
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Abstract (arXiv)
Resolving Design Rule Violations (DRVs) in layouts entails an iterative loop of geometric edits and verification. We present DRC-Aid, a closed-loop agentic framework that automates local DRC repair by formulating it as verification-in-the-loop search. To constrain the combinatorial geometric repair space, a deterministic Rule Engine converts physical verification tool-reported violations into a bounded menu of geometric edits. An off-the-shelf Large Language Model (LLM) evaluates local geometric context to select edits from this menu, with budgeted depth-first search and backtracking. Immediate feedback from verification tools such as Calibre nmDRC/nmLVS enforces geometric compliance and guards against electrical-topology degradation, while a global Memory Bank prevents cyclic re-exploration. Evaluated on FreePDK45 layouts containing DRVs, DRC-Aid achieves DRC-clean, LVS-equivalent repairs in ~92.5% of cases with a ~98% total violation reduction, while residual cases yield partially repaired LVS-equivalent candidates. Under an identical search and verification infrastructure, LLM-based selection outperforms random (54.4%) and deterministic-heuristic (83.3%) policies, with the gap widening on cases with six or more violations.
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References · 4
- 2023Efficient Memory Management for Large Language Model Serving with PagedAttentioncited by 5,944
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Promptscited by 4
- 2025PGR-DRC: Pre-Global Routing DRC Violation Prediction Using Unsupervised Learningcited by 1
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- 2026EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
- 2026SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
- 2026Rule2DRC: Benchmarking LLM Agents for DRC Script Synthesis with Execution-Guided Test Generation
- 2026Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing
- 2026Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair
- 2026DRCY: Agentic Hardware Design Reviews
- 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
- 2025VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair