mlsanityData to 7 Oct 2026

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement

arXiv 2606.19387 ↗First posted 16 Jun 2026cs.SE cs.AIcited by 0

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Abstract (arXiv)

Large language models (LLMs) have achieved remarkable success in software development. However, they are susceptible to hallucinations, meaning that they can introduce subtle semantic and logical errors. Due to the high stakes in chip design and manufacturing, hardware engineers are still reluctant to rely on LLMs for register-transfer level (RTL) generation. In this paper, we propose a hardware generation framework that combines the creativity and broad knowledge of LLMs with the explainability and mathematical rigor of formal methods. Specifically, we devise a set of transformation rules that cover various design decisions and hardware features. By iteratively applying these rules, an LLM agent can convert a design specification into an RTL program with guaranteed correctness. Experimental results demonstrate the effectiveness and efficiency of the framework.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 13 of its 46 references that are in the map. First posted on arXiv 16 Jun 2026.

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13 of 46 references.

References · 13

  1. 2024RULER: What's the Real Context Size of Your Long-Context Language Models?cited by 1,270
  2. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  3. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  4. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  5. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  6. 2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 17
  7. 2024C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gapcited by 16
  8. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  9. 2025Automated Multi-Agent Workflows for RTL Designcited by 3
  10. 2017The Refinement Calculus of Reactive Systems Toolsetcited by 2
  11. 2014Automata Describing Object Behaviorcited by 1
  12. 2016Programming Language Features for Refinementcited by 1
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  1. 2017The Refinement Calculus of Reactive Systemscited by 1

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  1. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow
  2. 2026A Survey on LLM-Integrated Hardware Design Verification
  3. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  4. 2026Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair
  5. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  6. 2026How LLMs Fail and Generalize in RTL Coding for Hardware Design?
  7. 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
  8. 2026LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation