mlsanityData to 7 Oct 2026

TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator

arXiv 2503.05951 ↗First posted 7 Mar 2025cs.AR cs.AIcited by 2

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Abstract (arXiv)

The increasing complexity and scale of Deep Neural Networks (DNNs) necessitate specialized tensor accelerators, such as Tensor Processing Units (TPUs), to meet various computational and energy efficiency requirements. Nevertheless, designing optimal TPU remains challenging due to the high domain expertise level, considerable manual design time, and lack of high-quality, domain-specific datasets. This paper introduces TPU-Gen, the first Large Language Model (LLM) based framework designed to automate the exact and approximate TPU generation process, focusing on systolic array architectures. TPU-Gen is supported with a meticulously curated, comprehensive, and open-source dataset that covers a wide range of spatial array designs and approximate multiply-and-accumulate units, enabling design reuse, adaptation, and customization for different DNN workloads. The proposed framework leverages Retrieval-Augmented Generation (RAG) as an effective solution for a data-scare hardware domain in building LLMs, addressing the most intriguing issue, hallucinations. TPU-Gen transforms high-level architectural specifications into optimized low-level implementations through an effective hardware generation pipeline. Our extensive experimental evaluations demonstrate superior performance, power, and area efficiency, with an average reduction in area and power of 92% and 96% from the manual optimization reference values. These results set new standards for driving advancements in next-generation design automation tools powered by LLMs.

Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 26 of its 49 references that are in the map. First posted on arXiv 7 Mar 2025.

Builds on

26 of 49 references.

References · 26

  1. 2022Atlas: Few-shot Learning with Retrieval Augmented Language Modelscited by 940
  2. 2023Benchmarking Large Language Models in Retrieval-Augmented Generationcited by 307
  3. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  4. 2022Why Can GPT Learn In-Context? Language Models Implicitly Perform Gradient Descent as Meta-Optimizerscited by 204
  5. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  6. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  7. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  8. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  9. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  10. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  11. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  12. 2019Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integrationcited by 59
14 more
  1. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  2. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  3. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  4. 2024A Survey on Large Language Model Hallucination via a Creativity Perspectivecited by 38
  5. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 30
  6. 2022A Survey on Collaborative DNN Inference for Edge Intelligencecited by 23
  7. 2024Mitigating Hallucinations in Large Language Models via Self-Refinement-Enhanced Knowledge Retrievalcited by 16
  8. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 16
  9. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
  10. 2024Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architecturescited by 12
  11. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  12. 2024SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generationcited by 9
  13. 2020New Approximate Multiplier for Low Power Digital Signal Processingcited by 2
  14. 2022A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networkscited by 1

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 2.

2 papers.

  1. 2026AI+HW 2035: Shaping the Next Decadecited by 1
  2. 2026PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devicescited by 0

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  1. 2025Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs
  2. 2026Ragged Paged Attention: A High-Performance and Flexible LLM Inference Kernel for TPU
  3. 2019Benchmarking TPU, GPU, and CPU Platforms for Deep Learning
  4. 2026TCL: Enabling Fast and Efficient Cross-Hardware Tensor Program Optimization via Continual Learning
  5. 2024vTensor: Flexible Virtual Tensor Management for Efficient LLM Serving
  6. 2026Rethinking the Role of Tensor Decompositions in Post-Training LLM Compression
  7. 2024JORA: JAX Tensor-Parallel LoRA Library for Retrieval Augmented Fine-Tuning
  8. 2022Moses: Efficient Exploitation of Cross-device Transferable Features for Tensor Program Optimization