mlsanityData to 14 Oct 2026

SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specifications

arXiv 2609.33699 ↗First posted 27 Sep 2026cs.AI cs.SEcited by 0

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Abstract (arXiv)

Existing benchmarks for large language models (LLMs) in hardware design evaluate downstream artifacts such as generated RTL, assertions, or testbenches. When a model fails such a benchmark, the failure is ambiguous: it may have misread the specification, or it may have understood the specification and failed to write the code. We present SpecRead, a benchmark that isolates specification comprehension from generation ability. SpecRead v2.1 contains 385 questions over 10 open-source OpenTitan IP blocks: exact retrieval, cross-section reasoning, contradiction detection in mutated specifications, and spec-RTL consistency checking, plus 82 controls (41 distractor, 41 consistent-RTL). Type-4 items are built from real RTL mutations; we retain only mutations that Icarus Verilog simulation shows to change observable behavior. A with-spec vs. without-spec ablation suggests the questions require the excerpt, not training recall alone (without-spec accuracy 3/20 on the t1/t2 subset), though memorization of the source text may still help spot mutations. As an initial characterization with a small model, Ministral-3B scores 33.2% overall (128/385; macro average 39.0%): 55.2% on retrieval, 51.7% on cross-section reasoning. On the two contradiction-focused types, the verdict-plus-location measure gives 48.0% (t3) and 63.3% (t4), with a 51.2% false-positive rate on distractors and 100% on consistent-RTL controls. Layered scoring shows the model locates contradictions well (78.9-81.6% location accuracy) but scores lower on their category (43.9-49.7%). A structured "rule-table" prompting intervention lowers accuracy on every question type except t2 (tied). SpecRead is automatically scorable by deterministic checks, with gray-zone cases counted wrong under the conservative main scoring. The benchmark is regenerable for type-3 items via mutation injection, and built exclusively from public sources.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 19 of its 23 references that are in the map. First posted on arXiv 27 Sep 2026.

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References · 19

  1. 2021Dynabench: Rethinking Benchmarking in NLPcited by 459
  2. 2021SummaC: Re-Visiting NLI-based Models for Inconsistency Detection in Summarizationcited by 407
  3. 2024LiveBench: A Challenging, Contamination-Limited LLM Benchmarkcited by 262
  4. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  5. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  6. 2021ContractNLI: A Dataset for Document-level Natural Language Inference for Contractscited by 148
  7. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  8. 2021DocNLI: A Large-scale Dataset for Document-level Natural Language Inferencecited by 75
  9. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 44
  10. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  11. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  12. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
7 more
  1. 2020Natural Language Inference in Context -- Investigating Contextual Reasoning over Long Textscited by 23
  2. 2024Ask-EDA: A Design Assistant Empowered by LLM, Hybrid RAG and Abbreviation De-hallucinationcited by 14
  3. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 13
  4. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  5. 2026AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specificationscited by 3
  6. 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
  7. 2026VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generationcited by 1

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