mlsanityData to 14 Oct 2026

ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation

arXiv 2402.00093 ↗First posted 31 Jan 2024cs.SE cs.LGcited by 16

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Abstract (arXiv)

System Verilog Assertion (SVA) formulation -- a critical yet complex task is a prerequisite in the Assertion Based Verification (ABV) process. Traditionally, SVA formulation involves expert-driven interpretation of specifications, which is time-consuming and prone to human error. Recently, LLM-informed automatic assertion generation is gaining interest. We designed a novel framework called ChIRAAG, based on OpenAI GPT4, to generate SVA from natural language specifications of a design. ChIRAAG constitutes the systematic breakdown of design specifications into a standardized format, further generating assertions from formatted specifications using LLM. Furthermore, we used few test cases to validate the LLM-generated assertions. Automatic feedback of log messages from the simulation tool to the LLM ensures that the framework can generate correct SVAs. In our experiments, only 27% of LLM-generated raw assertions had errors, which was rectified in few iterations based on the simulation log. Our results on OpenTitan designs show that LLMs can streamline and assist engineers in the assertion generation process, reshaping verification workflows.

Key facts. Cited by 16 papers in the map (data through 14 Oct 2026). Builds on 22 of its 41 references that are in the map. First posted on arXiv 31 Jan 2024.

Builds on

22 of 41 references.

References · 22

  1. 2023GPT-4 Technical Reportcited by 18,396
  2. 2023Llama 2: Open Foundation and Fine-Tuned Chat Modelscited by 13,028
  3. 2021Evaluating Large Language Models Trained on Codecited by 8,320
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  11. 2022Large Language Models are Zero-Shot Fuzzers: Fuzzing Deep-Learning Libraries via Large Language Modelscited by 103
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10 more
  1. 202314 Examples of How LLMs Can Transform Materials Science and Chemistry: A Reflection on a Large Language Model Hackathoncited by 86
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  5. 2023LLM-Prop: Predicting Physical And Electronic Properties Of Crystalline Solids From Their Text Descriptionscited by 29
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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 3; 2025: 6; 2026: 7.

16 papers.

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  1. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
  2. 2024AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generationcited by 16
  3. 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
  4. 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
  5. 2025Are LLMs Ready for Practical Adoption for Assertion Generation?cited by 6
  6. 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVAcited by 6
  7. 2026ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMscited by 6
  8. 2026Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protectioncited by 3
  9. 2026Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verificationcited by 3
  10. 2025SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refinecited by 2
  11. 2025SVAgent: AI Agent for Hardware Security Verification Assertioncited by 1
  12. 2026FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verificationcited by 1
4 more
  1. 2026SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generationcited by 1
  2. 2025DUET: Agentic Design Understanding via Experimentation and Testingcited by 0
  3. 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verificationcited by 0
  4. 2026A Survey on LLM-Integrated Hardware Design Verificationcited by 0