mlsanityData to 7 Oct 2026

Are LLMs Any Good for High-Level Synthesis?

arXiv 2408.10428 ↗First posted 19 Aug 2024cs.AR cs.AIcited by 6

Not on the map. Why?

Abstract (arXiv)

The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.

Key facts. Cited by 6 papers in the map (data through 7 Oct 2026). Builds on 14 of its 30 references that are in the map. First posted on arXiv 19 Aug 2024.

Builds on

14 of 30 references.

References · 14

  1. 2019Green AIcited by 620
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  3. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  4. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  5. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  6. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  7. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
  8. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 25
  9. 2024AMSNet: Netlist Dataset for AMS Circuitscited by 24
  10. 2023Using LLMs to Facilitate Formal Verification of RTLcited by 17
  11. 2024LLM-Aided Testbench Generation and Bug Detection for Finite-State Machinescited by 15
  12. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 14
2 more
  1. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  2. 2023Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Designcited by 2

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 4; 2026: 2.

6 papers.

  1. 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
  2. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  3. 2025TFHE-Coder: Evaluating LLM-agentic Fully Homomorphic Encryption Code Generationcited by 4
  4. 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generationcited by 2
  5. 2025Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimizationcited by 0
  6. 2026Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Designcited by 0