mlsanityData to 14 Oct 2026

On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators

arXiv 2306.06923 ↗First posted 12 Jun 2023cs.LG cs.ARcited by 11

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Abstract (arXiv)

Deep Neural Networks (DNNs) have demonstrated impressive performance across a wide range of tasks. However, deploying DNNs on edge devices poses significant challenges due to stringent power and computational budgets. An effective solution to this issue is software-hardware (SW-HW) co-design, which allows for the tailored creation of DNN models and hardware architectures that optimally utilize available resources. However, SW-HW co-design traditionally suffers from slow optimization speeds because their optimizers do not make use of heuristic knowledge, also known as the ``cold start'' problem. In this study, we present a novel approach that leverages Large Language Models (LLMs) to address this issue. By utilizing the abundant knowledge of pre-trained LLMs in the co-design optimization process, we effectively bypass the cold start problem, substantially accelerating the design process. The proposed method achieves a significant speedup of 25x. This advancement paves the way for the rapid and efficient deployment of DNNs on edge devices.

Key facts. Cited by 11 papers in the map (data through 14 Oct 2026). Builds on 13 of its 20 references that are in the map. First posted on arXiv 12 Jun 2023.

Builds on

13 of 20 references.

References · 13

  1. 2020Language Models are Few-Shot Learnerscited by 32,419
  2. 2021Zero-Shot Text-to-Image Generationcited by 4,288
  3. 2018FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Searchcited by 485
  4. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  5. 2023Can GPT-4 Perform Neural Architecture Search?cited by 74
  6. 2019Hardware/Software Co-Exploration of Neural Architecturescited by 50
  7. 2019Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Searchcited by 38
  8. 2019Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Acceleratorscited by 32
  9. 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
  10. 2022SWIM: Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 16
  11. 2019When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remediescited by 15
  12. 2022Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?cited by 12
1 more
  1. 2019Design Automation for Efficient Deep Learning Computingcited by 4

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2023: 1; 2024: 5; 2025: 4; 2026: 1.

11 papers.

  1. 2024On-Device Language Models: A Comprehensive Reviewcited by 104
  2. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  3. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  4. 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 15
  5. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  6. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  7. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  8. 2024FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Modelscited by 9
  9. 2023Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Modelscited by 8
  10. 2024Towards Safer Heuristics With XPlaincited by 2
  11. 2026Energy Efficient Software Hardware CoDesign for Machine Learning: From TinyML to Large Language Modelscited by 0