BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection
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Abstract (arXiv)
The current landscape of system-on-chips (SoCs) security verification faces challenges due to manual, labor-intensive, and inflexible methodologies. These issues limit the scalability and effectiveness of security protocols, making bug detection at the Register-Transfer Level (RTL) difficult. This paper proposes a new framework named BugWhisperer that utilizes a specialized, fine-tuned Large Language Model (LLM) to address these challenges. By enhancing the LLM's hardware security knowledge and leveraging its capabilities for text inference and knowledge transfer, this approach automates and improves the adaptability and reusability of the verification process. We introduce an open-source, fine-tuned LLM specifically designed for detecting security vulnerabilities in SoC designs. Our findings demonstrate that this tailored LLM effectively enhances the efficiency and flexibility of the security verification process. Additionally, we introduce a comprehensive hardware vulnerability database that supports this work and will further assist the research community in enhancing the security verification process.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Builds on 7 of its 17 references that are in the map. First posted on arXiv 28 May 2025.
Builds on
7 of 17 references.
References · 7
- 2023GPT-4 Technical Reportcited by 18,396
- 2024The Llama 3 Herd of Modelscited by 14,715
- 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,380
- 2023Code Llama: Open Foundation Models for Codecited by 2,139
- 2023ChipGPT: How far are we from natural language hardware designcited by 105
- 2023LLM for SoC Security: A Paradigm Shiftcited by 22
- 2024Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verificationcited by 11
Built on by
Citing papers per year: 2025: 1; 2026: 4.
5 papers.
- 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Modelscited by 6
- 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilogcited by 2
- 2026LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verificationcited by 1
- 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detectioncited by 0
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models23 Apr 2026
- 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog15 Apr 2026
- 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection5 Mar 2026
- 2026LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification6 Jan 2026
- 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models25 Jun 2025