mlsanityData to 14 Oct 2026

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction

arXiv 2504.19099 ↗First posted 27 Apr 2025cs.SE cs.AI cs.ARcited by 12

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Abstract (arXiv)

Large Language Models (LLMs) have demonstrated remarkable potential in debugging for various programming languages. However, the application of LLMs to Verilog debugging remains insufficiently explored. Here, we present VeriDebug, an approach that integrates contrastive representation and guided correction capabilities for automated Verilog debugging. Unlike existing methods, VeriDebug employs an embedding-based technique to accurately retrieve internal information, followed by bug-fixing. VeriDebug unifies Verilog bug detection and correction through a shared parameter space. By simultaneously learning bug patterns and fixes, it streamlines debugging via contrastive embedding and guided correction. Empirical results show the efficacy of VeriDebug in enhancing Verilog debugging. Our VeriDebugLoc, Type model achieves 64.7 accuracy in bug fixing (Acc1), a significant improvement from the existing open-source SOTAs 11.3. This performance not only outperforms open-source alternatives but also exceeds larger closed-source models like GPT-3.5-turbo (36.6), offering a more accurate alternative to conventional debugging methods.

Key facts. Cited by 12 papers in the map (data through 14 Oct 2026). Builds on 15 of its 22 references that are in the map. First posted on arXiv 27 Apr 2025.

Builds on

15 of 22 references.

References · 15

  1. 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,297
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2020Scaling Laws for Neural Language Modelscited by 6,586
  4. 2023Retrieval-Augmented Generation for Large Language Models: A Surveycited by 2,212
  5. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,181
  6. 2022Text and Code Embeddings by Contrastive Pre-Trainingcited by 361
  7. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  8. 2024Generative Representational Instruction Tuningcited by 233
  9. 2024Debug like a Human: A Large Language Model Debugger via Verifying Runtime Execution Step-by-stepcited by 127
  10. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  11. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  12. 2024Scaling Retrieval-Based Language Models with a Trillion-Token Datastorecited by 56
3 more
  1. 2022Multilingual Generative Language Models for Zero-Shot Cross-Lingual Event Argument Extractioncited by 40
  2. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  3. 2024CoLLEGe: Concept Embedding Generation for Large Language Modelscited by 3

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 6; 2026: 6.

12 papers.

  1. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  2. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  3. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 7
  4. 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Modelscited by 6
  5. 2025FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failurescited by 5
  6. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  7. 2026InCoder-32B-Thinking: Industrial Code World Model for Thinkingcited by 4
  8. 2026CktEvo: Repository-Level RTL Code Benchmark for Design Evolutioncited by 3
  9. 2025Learning to Debug: LLM-Organized Knowledge Trees for Solving RTL Assertion Failurescited by 1
  10. 2026VeriPilot: An LLM-Powered Verilog Debugging Frameworkcited by 1
  11. 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answeringcited by 0
  12. 2026Benchmarking LLMs for Verilog Design Flowscited by 0