mlsanityData to 14 Oct 2026

GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification

arXiv 2508.19393 ↗First posted 26 Aug 2025cs.AR cs.LGcited by 2

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Abstract (arXiv)

Analog subcircuit identification is a core task in analog design, essential for simulation, sizing, and layout. Traditional methods often require extensive human expertise, rule-based encoding, or large labeled datasets. To address these challenges, we propose GENIE-ASI, the first training-free, large language model (LLM)-based methodology for analog subcircuit identification. GENIE-ASI operates in two phases: it first uses in-context learning to derive natural language instructions from a few demonstration examples, then translates these into executable Python code to identify subcircuits in unseen SPICE netlists. In addition, to evaluate LLM-based approaches systematically, we introduce a new benchmark composed of operational amplifier netlists (op-amps) that cover a wide range of subcircuit variants. Experimental results on the proposed benchmark show that GENIE-ASI matches rule-based performance on simple structures (F1-score = 1.0), remains competitive on moderate abstractions (F1-score = 0.81), and shows potential even on complex subcircuits (F1-score = 0.31). These findings demonstrate that LLMs can serve as adaptable, general-purpose tools in analog design automation, opening new research directions for foundation model applications in analog design automation.

Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 20 of its 38 references that are in the map. First posted on arXiv 26 Aug 2025.

Builds on

20 of 38 references.

References · 20

  1. 2023GPT-4 Technical Reportcited by 18,396
  2. 2023LLaMA: Open and Efficient Foundation Language Modelscited by 14,132
  3. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
  4. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
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  6. 2022A Survey on In-context Learningcited by 721
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  8. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  9. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  10. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 84
  11. 2024What's Wrong with Your Code Generated by Large Language Models? An Extensive Studycited by 53
  12. 2024AnyGraph: Graph Foundation Model in the Wildcited by 53
8 more
  1. 2024Beyond Instruction Following: Evaluating Inferential Rule Following of Large Language Modelscited by 23
  2. 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Modelscited by 18
  3. 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
  4. 2024Schemato -- An LLM for Netlist-to-Schematic Conversioncited by 11
  5. 2020A general approach for identifying hierarchical symmetry constraints for analog circuit layoutcited by 9
  6. 2024SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detectioncited by 7
  7. 2020A Functional Block Decomposition Method for Automatic Op-Amp Designcited by 2
  8. 2021FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmpositioncited by 2

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 1; 2026: 1.

2 papers.