mlsanityData to 14 Oct 2026

SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation

arXiv 2603.08719 ↗First posted 10 Feb 2026cs.AR cs.AI cs.SEcited by 4

On the map: LLM reasoning → Reasoning for agents, planning and code

also in 1 more
Abstract (arXiv)

Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.

Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Placed in Reasoning for agents, planning and code, one of 17 directions in LLM reasoning. Builds on 29 of its 36 references that are in the map. First posted on arXiv 10 Feb 2026.

Builds on

29 of 36 references.

Closest ancestors · 3

Same direction, newest first

  1. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation30 May
  2. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation17 May
  3. 2024Qwen2.5-Coder Technical Report18 Sep

Other references · 26

  1. 2025Qwen3 Technical Reportcited by 8,820
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
  4. 2023Efficient Memory Management for Large Language Model Serving with PagedAttentioncited by 5,944
  5. 2023MetaGPT: Meta Programming for A Multi-Agent Collaborative Frameworkcited by 1,808
  6. 2025gpt-oss-120b & gpt-oss-20b Model Cardcited by 1,386
  7. 2025s1: Simple test-time scalingcited by 1,341
  8. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,181
  9. 2024OLMo: Accelerating the Science of Language Modelscited by 613
  10. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  11. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  12. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
14 more
  1. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  2. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  3. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 44
  4. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  5. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  6. 2023L2CEval: Evaluating Language-to-Code Generation Capabilities of Large Language Modelscited by 22
  7. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  8. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  9. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  10. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  11. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  12. 2025Efficient Code Embeddings from Code Generation Modelscited by 13
  13. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
  14. 2025QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Designcited by 1

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 4.

4 papers.

  1. 2026From Question Answering to Task Completion: A Survey on Agent System and Harness Designcited by 12
  2. 2026Exploring the Agentic Frontier of Verilog Code Generationcited by 1
  3. 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generationcited by 1
  4. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  2. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
  3. 2024RGD: Multi-LLM Based Agent Debugger via Refinement and Generation Guidance
  4. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  5. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
  6. 2026Automating Formal Verification with Agent-Guided Tree Search
  7. 2026No Test Cases, No Problem: Distillation-Driven Code Generation for Scientific Workflows
  8. 2025Enhancing LLM Code Generation: A Systematic Evaluation of Multi-Agent Collaboration and Runtime Debugging for Improved Accuracy, Reliability, and Latency