mlsanityData to 7 Oct 2026

Can Agents Design Better Chips with a Higher Level Abstraction?

arXiv 2609.21157 ↗First posted 17 Sep 2026cs.AI cs.ARcited by 0

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6× geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at https://github.com/ZijD/AHRR.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 14 of its 34 references that are in the map. First posted on arXiv 17 Sep 2026.

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14 of 34 references.

Closest ancestors · 3

Same direction, newest first

  1. 2026AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance29 Jun
  2. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation10 Dec
  3. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool15 Aug

Other references · 11

  1. 2024The Llama 3 Herd of Modelscited by 14,192
  2. 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,355
  3. 2023Efficient Memory Management for Large Language Model Serving with PagedAttentioncited by 5,767
  4. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  5. 2025LServe: Efficient Long-sequence LLM Serving with Unified Sparse Attentioncited by 41
  6. 2021ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representationcited by 21
  7. 2024Allo: A Programming Model for Composable Accelerator Designcited by 16
  8. 2025LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuningcited by 8
  9. 2025FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failurescited by 4
  10. 2025Holistic Optimization Framework for FPGA Acceleratorscited by 3
  11. 2026FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Designcited by 3

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  1. 2026From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis
  2. 2025ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
  3. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
  4. 2024Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)
  5. 2026ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design
  6. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
  7. 2025RTLSquad: Multi-Agent Based Interpretable RTL Design
  8. 2025Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective