mlsanityData to 7 Oct 2026

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

arXiv 2312.08617 ↗First posted 14 Dec 2023cs.PL cs.ARcited by 69

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Abstract (arXiv)

The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. However, most existing approaches heavily rely on commercial LLMs such as ChatGPT, while open-source LLMs tailored for this specific design generation task exhibit notably inferior performance. The absence of high-quality open-source solutions restricts the flexibility and data privacy of this emerging technique. In this study, we present a new customized LLM solution with a modest parameter count of only 7B, achieving better performance than GPT-3.5 on all representative benchmarks for RTL code generation. Especially, it outperforms GPT-4 in VerilogEval Machine benchmark. This remarkable balance between accuracy and efficiency is made possible by leveraging our new RTL code dataset and a customized LLM algorithm, both of which have been made fully open-source.

Key facts. Cited by 69 papers in the map (data through 7 Oct 2026). First posted on arXiv 14 Dec 2023.

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 18; 2025: 36; 2026: 15.

69 papers.

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  1. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  2. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  3. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  4. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  5. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  6. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  7. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  8. 2024AMSNet: Netlist Dataset for AMS Circuitscited by 24
  9. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  10. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  11. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  12. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
38 more
  1. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  2. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  3. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  4. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  5. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  6. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMscited by 12
  7. 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 11
  8. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  9. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  10. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  11. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  12. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  13. 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
  14. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  15. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
  16. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentationcited by 7
  17. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  18. 2025Evolution of Optimization Algorithms for Global Placement via Large Language Modelscited by 6
  19. 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agentscited by 6
  20. 2024SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Modelcited by 4
  21. 2025HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionscited by 4
  22. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
  23. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  24. 2024The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimationcited by 3
  25. 2025RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Frameworkcited by 3
  26. 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
  27. 2025Automated Multi-Agent Workflows for RTL Designcited by 3
  28. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
  29. 2025Speculative Decoding for Verilog: Speed and Quality, All in Onecited by 2
  30. 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
  31. 2025SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chipcited by 2
  32. 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimizationcited by 2
  33. 2024ChipXplore: Natural Language Exploration of Hardware Designs and Librariescited by 1
  34. 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
  35. 2025HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databasescited by 1
  36. 2025MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debuggingcited by 1
  37. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  38. 2025AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testingcited by 1

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