mlsanityData to 7 Oct 2026

TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation

arXiv 2511.15767 ↗First posted 19 Nov 2025cs.LG cs.AI cs.PLcited by 3

On the map: LLM alignment / RLHF / preference optimisation → Process reward models for reasoning

Abstract (arXiv)

With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification remains the most time-consuming and resource-intensive phase, where generating effective stimuli for the design under test (DUT) is both critical and labor-intensive. We present it TB or not TB, a framework for automated stimulus generation using LLMs fine-tuned through Coverage-Driven Direct Preference Optimization (CD-DPO). To enable preference-based training, we introduce PairaNet, a dataset derived from PyraNet that pairs high- and low-quality testbenches labeled using simulation-derived coverage metrics. The proposed CD-DPO method integrates quantitative coverage feedback directly into the optimization objective, guiding the model toward generating stimuli that maximize verification coverage. Experiments on the CVDP CID12 benchmark show that it TB or not TB outperforms both open-source and commercial baselines, achieving up to 77.27% improvement in code coverage, demonstrating the effectiveness of Coverage-driven preference optimization for LLM-based hardware verification.

Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). Placed in Process reward models for reasoning, one of 10 directions in LLM alignment / RLHF / preference optimisation. Builds on 22 of its 30 references that are in the map. First posted on arXiv 19 Nov 2025.

Builds on

22 of 30 references.

References · 22

  1. 2017Attention Is All You Needcited by 59,932
  2. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
  3. 2023Direct Preference Optimization: Your Language Model is Secretly a Reward Modelcited by 7,916
  4. 2019Fine-Tuning Language Models from Human Preferencescited by 2,124
  5. 2024Scaling LLM Test-Time Compute Optimally can be More Effective than Scaling Model Parameterscited by 1,928
  6. 2024SimPO: Simple Preference Optimization with a Reference-Free Rewardcited by 951
  7. 2024β-DPO: Direct Preference Optimization with Dynamic βcited by 89
  8. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  9. 2024WPO: Enhancing RLHF with Weighted Preference Optimizationcited by 53
  10. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 41
  11. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
  12. 2024AlphaDPO: Adaptive Reward Margin for Direct Preference Optimizationcited by 27
10 more
  1. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 23
  2. 2024RainbowPO: A Unified Framework for Combining Improvements in Preference Optimizationcited by 19
  3. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  4. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 16
  5. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
  6. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  7. 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
  8. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
  9. 2024Multi-Preference Optimization: Generalizing DPO via Set-Level Contrastscited by 9
  10. 2025KL Penalty Control via Perturbation for Direct Preference Optimizationcited by 5

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 3.

3 papers.

  1. 2026LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generationcited by 4
  2. 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMscited by 1
  3. 2026CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learningcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
  2. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
  3. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
  4. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
  5. 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generation
  6. 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
  7. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  8. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation