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RTLCurator: Label-Efficient Data Curation for RTL Generation

arXiv 2607.29283 ↗First posted 31 Jul 2026cs.AR cs.LGcited by 0

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Abstract (arXiv)

Training large language models (LLMs) to write register-transfer level (RTL) requires large corpora of paired specifications and code, and such data is scarce enough that most public corpora are now synthesized. Synthesis provides scale but not correctness, and in two widely used RTL datasets only 24.4% and 53.5% of pairs pass generated functional tests. This raises the question of how much of such a corpus to keep and which part of it. Correctness alone is a poor answer. A pair that misbehaves in one corner case still shows valid syntax and interface conventions, and complex sequential designs are both harder to generate and harder to validate, so filtering by correctness leaves a corpus of short and simple modules. Correctness is also hard to obtain, since behavior leaves little trace on the surface in RTL, and validating an entire corpus only sorts pairs into passed and failed. We present RTLCurator, which learns a behavior-aware compatibility prior by contrasting each specification with implementations that fail simulation, and calibrates it to a new corpus using a small number of validated pairs. It then constructs the retained subset by balancing alignment, representation coverage, and RTL structural richness. On CodeV and RTLCoder, keeping 80% of the corpus this way improves on training with the full corpus across all reported metrics while validating only 10% of the pool, whereas ranking by the score alone falls below random selection and filtering the whole pool by simulation does no better.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 18 of its 23 references that are in the map. First posted on arXiv 31 Jul 2026.

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References · 18

  1. 2024LESS: Selecting Influential Data for Targeted Instruction Tuningcited by 532
  2. 2023What Makes Good Data for Alignment? A Comprehensive Study of Automatic Data Selection in Instruction Tuningcited by 364
  3. 2022The Stack: 3 TB of permissively licensed source codecited by 359
  4. 2019Deep Semi-Supervised Anomaly Detectioncited by 291
  5. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  6. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  7. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  8. 2025Seed-Coder: Let the Code Model Curate Data for Itselfcited by 49
  9. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  10. 2024Improving Data Efficiency via Curating LLM-Driven Rating Systemscited by 29
  11. 2022Meta-Query-Net: Resolving Purity-Informativeness Dilemma in Open-set Active Learningcited by 25
  12. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
6 more
  1. 2025CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Designcited by 14
  2. 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10
  3. 2025Towards A Generalist Code Embedding Model Based On Massive Data Synthesiscited by 8
  4. 2025UnitCoder: Scalable Iterative Code Synthesis with Unit Test Guidancecited by 7
  5. 2023Active Code Learning: Benchmarking Sample-Efficient Training of Code Modelscited by 3
  6. 2026Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curationcited by 2

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