VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
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Abstract (arXiv)
Rapid advances in language models (LMs) have created new opportunities for automated code generation while complicating trade-offs between model characteristics and prompt design choices. In this work, we provide an empirical map of recent trends in LMs for Verilog code generation, focusing on interactions among model reasoning, specialization, and prompt engineering strategies. We evaluate a diverse set of small and large LMs, including general-purpose, reasoning, and domain-specific variants. Our experiments use a controlled factorial design spanning benchmark prompts, structured outputs, prompt rewriting, chain-of-thought reasoning, in-context learning, and evolutionary prompt optimization via Genetic-Pareto. Across two Verilog benchmarks, we identify patterns in how model classes respond to structured prompts and optimization, and we document which trends generalize across LMs and benchmarks versus those that are specific to particular model-prompt combinations.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 23 of its 28 references that are in the map. First posted on arXiv 4 Feb 2026.
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23 of 28 references.
References · 23
- 2020Language Models are Few-Shot Learnerscited by 32,419
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11 more
- 2023Structured Chain-of-Thought Prompting for Code Generationcited by 138
- 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
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- 2026SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence ↗
- 2025VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning
- 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
- 2026Prompt Codebooks: Discrete Compositional Optimization for Language Model Instruction Refinement