mlsanityData to 14 Oct 2026

Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language

arXiv 2503.11662 ↗First posted 14 Feb 2025cs.AR cs.AI cs.CLcited by 0

Not on the map. Why?

Abstract (arXiv)

In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level models, which often lack accuracy, or trial synthesis, which is both labor-intensive and time-consuming. We introduce a new methodology, called Lorecast, which accepts English prompts as input to rapidly generate layout-aware performance and power estimates. This approach bypasses the need for HDL code development and synthesis, making it both fast and user-friendly. Experimental results demonstrate that Lorecast achieves accuracy within a few percent of error compared to post-layout analysis, while significantly reducing turnaround time.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 36 of its 61 references that are in the map. First posted on arXiv 14 Feb 2025.

Builds on

36 of 61 references.

References · 36

  1. 2017Attention Is All You Needcited by 60,361
  2. 2020Language Models are Few-Shot Learnerscited by 32,419
  3. 2023GPT-4 Technical Reportcited by 18,396
  4. 2024The Llama 3 Herd of Modelscited by 14,715
  5. 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,297
  6. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  7. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
  8. 2021On the Opportunities and Risks of Foundation Modelscited by 4,033
  9. 2024Gemini 1.5: Unlocking multimodal understanding across millions of tokens of contextcited by 3,224
  10. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  11. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  12. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
24 more
  1. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  2. 2023Structured Chain-of-Thought Prompting for Code Generationcited by 138
  3. 2023An Empirical Study of the Non-determinism of ChatGPT in Code Generationcited by 137
  4. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  5. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  6. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  7. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  8. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  9. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  10. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  11. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  12. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  13. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  14. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  15. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  16. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  17. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
  18. 2023MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Designcited by 19
  19. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
  20. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  21. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 17
  22. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
  23. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  24. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 13

Built on by

Not cited yet.