mlsanityData to 14 Oct 2026

SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation

arXiv 2604.27238 ↗First posted 29 Apr 2026cs.CR cs.ARcited by 2

On the map: LLM safety and security → Safety alignment, refusal and guardrails

Abstract (arXiv)

As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly assembled or generated training data. These datasets frequently lack security verification and are highly susceptible to data poisoning attacks. Such poisoning can cause models to generate syntactically valid but insecure hardware modules that bypass standard functionality checks. To address this, we present SafeTune, a framework designed to harden LLM-based RTL generation against poisoning, specifically focusing on hardware Trojan (HT) insertion. SafeTune integrates two core components: (i) a Graph Neural Network (GNN) that models structural properties to identify anomalous circuitry patterns during fine-tuning, and (ii) a semantic verification module using text embeddings and an XGBoost classifier to assess prompt security. By coupling structural and semantic knowledge, SafeTune effectively filters poisoned inputs without sacrificing legitimate data. Experimental results demonstrate that SafeTune significantly enhances the robustness and reliability of LLM fine-tuning without requiring modifications to the underlying model architecture.

Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Placed in Safety alignment, refusal and guardrails, one of 12 directions in LLM safety and security. Builds on 25 of its 30 references that are in the map. First posted on arXiv 29 Apr 2026.

Builds on

25 of 30 references.

References · 25

  1. 2023Towards General Text Embeddings with Multi-stage Contrastive Learningcited by 723
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  3. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  4. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  5. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  6. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  7. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 44
  8. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  9. 2024PoisonBench: Assessing Large Language Model Vulnerability to Data Poisoningcited by 33
  10. 2023(Security) Assertions by Large Language Modelscited by 32
  11. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  12. 2024Embedding-based classifiers can detect prompt injection attackscited by 27
13 more
  1. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  2. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  3. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  4. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  5. 2023TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detectioncited by 9
  6. 2022Hardware Trojan Detection using Graph Neural Networkscited by 8
  7. 2024LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verificationcited by 7
  8. 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 5
  9. 2025LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardwarecited by 5
  10. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMscited by 5
  11. 2024Evolutionary Large Language Models for Hardware Security: A Comparative Surveycited by 4
  12. 2025CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakagecited by 3
  13. 2026MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generationcited by 2

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 2.

2 papers.

  1. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMscited by 0
  2. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection
  2. 2025When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation
  3. 2026RTLGuard: A Lightweight Teacher-Student Defense for Poisoned RTL Code Generation Models ↗
  4. 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
  5. 2024Root Defence Strategies: Ensuring Safety of LLM at the Decoding Level
  6. 2024Safety Layers in Aligned Large Language Models: The Key to LLM Security
  7. 2025Analysing Safety Risks in LLMs Fine-Tuned with Pseudo-Malicious Cyber Security Data
  8. 2025Fine-Tuning Lowers Safety and Disrupts Evaluation Consistency