mlsanityData to 7 Oct 2026

GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models

arXiv 2309.10730 ↗First posted 19 Sep 2023cs.LG cs.ARcited by 59

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Abstract (arXiv)

The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accelerators for various AI workloads remains both labor- and time-intensive. While existing design exploration and automation tools can partially alleviate the need for extensive human involvement, they still demand substantial hardware expertise, posing a barrier to non-experts and stifling AI accelerator development. Motivated by the astonishing potential of large language models (LLMs) for generating high-quality content in response to human language instructions, we embark on this work to examine the possibility of harnessing LLMs to automate AI accelerator design. Through this endeavor, we develop GPT4AIGChip, a framework intended to democratize AI accelerator design by leveraging human natural languages instead of domain-specific languages. Specifically, we first perform an in-depth investigation into LLMs' limitations and capabilities for AI accelerator design, thus aiding our understanding of our current position and garnering insights into LLM-powered automated AI accelerator design. Furthermore, drawing inspiration from the above insights, we develop a framework called GPT4AIGChip, which features an automated demo-augmented prompt-generation pipeline utilizing in-context learning to guide LLMs towards creating high-quality AI accelerator design. To our knowledge, this work is the first to demonstrate an effective pipeline for LLM-powered automated AI accelerator generation. Accordingly, we anticipate that our insights and framework can serve as a catalyst for innovations in next-generation LLM-powered design automation tools.

Key facts. Cited by 59 papers in the map (data through 7 Oct 2026). Builds on 27 of its 52 references that are in the map. First posted on arXiv 19 Sep 2023.

Builds on

27 of 52 references.

References · 27

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15 more
  1. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 876
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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 3; 2024: 19; 2025: 29; 2026: 8.

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  1. 2024Evolutionary Computation in the Era of Large Language Model: Survey and Roadmapcited by 89
  2. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  3. 2024Unveiling and Harnessing Hidden Attention Sinks: Enhancing Large Language Models without Training through Attention Calibrationcited by 70
  4. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  5. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  6. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
  7. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  8. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  9. 2024AMSNet: Netlist Dataset for AMS Circuitscited by 24
  10. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  11. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  12. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 21
38 more
  1. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  2. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  3. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  4. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  5. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  6. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  7. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
  8. 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 14
  9. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  10. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  11. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  12. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 12
  13. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  14. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  15. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  16. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  17. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  18. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  19. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
  20. 2024Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Modelscited by 6
  21. 2025Evolution of Optimization Algorithms for Global Placement via Large Language Modelscited by 6
  22. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 6
  23. 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Modelscited by 5
  24. 2024Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Modelscited by 4
  25. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4
  26. 2024Classification-Based Automatic HDL Code Generation Using LLMscited by 3
  27. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
  28. 2025Automated Multi-Agent Workflows for RTL Designcited by 3
  29. 2025CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Referencecited by 3
  30. 2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2
  31. 2025Evaluating LLM-based Workflows for Switched-Mode Power Supply Designcited by 2
  32. 2025OASIS: Outlier-Aware LUT-Based GEMM with Dual-Side Quantization for LLM Inference Accelerationcited by 2
  33. 2025HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databasescited by 1
  34. 2025Iceberg: Enhancing HLS Modeling with Synthetic Datacited by 1
  35. 2025A Multi-Agent Generative AI Framework for IC Module-Level Verification Automationcited by 1
  36. 2025MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debuggingcited by 1
  37. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  38. 2026Report for NSF Workshop on AI for Electronic Design Automationcited by 1

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